1. Suited for very small implementations (~$0.10 uCs, tiny FPGA softcores etc). But scales easily to high-performance cpus. 2. Clean slate design, applying lat

1. Suited for very small implementations (~$0.10 uCs, tiny FPGA softcores etc). But scales easily to high-performance cpus. 2. Clean slate design, applying latest insights concerning cpu design, virtualization & so on. 3. More a community effort & perhaps more open than other ISAs. OpenSPARC is (unlike early Sparc cpus) targeted at high-performance server / supercomputer chips. Similar for OpenPOWER which is mostly an IBM affair. And opened only around the time RISC-V came out. From what I've read (no personal experience), OpenRISC wasn't that well-designed or lacks RISC-Vs modularity. So a combination of license, community, ISA design & timing of its introduction.