What's a reasonable time ratio these days (as in Intel gen 13 and quality ddr5) to assume between an addition of registers and access to L3 and to RAM? Also, t

What's a reasonable time ratio these days (as in Intel gen 13 and quality ddr5) to assume between an addition of registers and access to L3 and to RAM? Also, they analyse gate times rather than ALU in estimations to account for someone producing a dedicated chip for cracking the cipher, right?