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Just waiting for the first post about programming this CPU to pop up on Stack Overflow ... :) It's quite an interesting architecture. From an initial perusal,
by unwind 15y ago
Just waiting for the first post about programming this CPU to pop up on Stack Overflow ... :)
It's quite an interesting architecture. From an initial perusal, I found these features note-worthy:
* Explicit access to PC as a register, makes "computed goto" trivial and very natural.
* Because of the above, there is no JMP instruction.
* Treating operations on registers as "values" makes the instruction set very orthogonal.
* No instructions for bit-manipulation.
* Lots of possible NOP instructions, like "SET PC,PC" (which I think should work, depends a bit on exactly when it's incremented but it looks safe).
* Word-addressed memory will make string processing interesting to implement. Maybe in space, everyone uses UTF-16.
* Single 64 K address space will put quite the limit on the amount of code, I guess the game will show how much code is needed to do anything.
* No I/O instructions means I/O must be memory-mapped, further reducing the space available for code. Maybe there will be bank-switching?
* No interrupts.
- TomFrost 15y ago> * Word-addressed memory will make string processing interesting to implement. Maybe in space, everyone uses UTF-16. Everyone in Minecraft, too -- almost. The string encoding in Minecraft's protocol spec is UCS-2, just a sneeze away from UTF-16. It seems Notch has a soft-spot for large encodings. It makes sense from a calculation and lookup perspective, but I wonder if the increased bandwidth and storage of 16-bit blocks has a measurable impact.
- ajuc 15y agoI think Java strings are UCS-2, so that explains why Minecraft uses this?
- ealloc 15y agoBy going UTF-16, he would make the game much more accessible to those not using a latin alphabet. If I was designing the game, I would favor internationalization vs space efficiency in the virtual computer. That way russian kids would get to have fun learning to write silly programs too.
- asdfaoeu 15y agoUTF-8 still has all the characters UTF-16 does it just uses more bytes to encode them. UTF-8 makes more sense if most of your characters can be represented in 8 bits.
- ealloc 15y agoyou can encode all characters in the basic multilingual plane with a single utf-16 code unit, while in utf-8 BMP characters have variable lengths from 1 to 3 bytes. If Notch only allows BMP characters and uses utf-16, internationalized string maniulation is very easy, as easy as ASCII for kids to mess with.
- cpeterso 15y agoIf the DCPU has only 64KB of RAM, encoding strings using UCS-2 or UTF-16 seems rather wasteful.
- nknight 15y agoWith cleverness, I could see the memory constraints being not so terribly constraining, even without a (real) bank switching mechanism. The reason we use "RAM" as we generally think of it is basically that other forms of storage are obscenely slow, right? In this case, however, our "mass storage" device would actually be... RAM. Just not directly-addressable RAM. Loading code and data from "disk" as-needed could be relatively fast. Edit: > No interrupts. Good catch, that's probably something we'll see added. I don't think Notch will like emulating a thousand polling CPUs... Edit 2: Just spotted this in Notch's twitter feed: https://twitter.com/#!/notch/status/187454444571598848 https://twitter.com/#!/notch/status/187454444571598848 "An emulator is coming Eventually(tm). I want to sort out some more IO design first, not release too early." So, I/O is still up in the air.
- wagabond 15y agoI'm a self-taught programmer, and don't know much about CPUs. Would someone mind putting this into relatively plain english, I'm quite curious to know the practical implications of this. Can we expect to see Python running on it in the near future for example :) ?
- nknight 15y agoAlthough some of the implications require experience to understand, I'd say it already is in "relatively plain English", you simply haven't been exposed to the vocabulary and concepts necessary. Trying to explain in any detail would basically be reproducing Wikipedia, so here are some links: http://en.wikipedia.org/wiki/Program_counter http://en.wikipedia.org/wiki/Program_counter http://en.wikipedia.org/wiki/Word_(computer_architecture) http://en.wikipedia.org/wiki/Word_(computer_architecture) http://en.wikipedia.org/wiki/JMP_(x86_instruction) http://en.wikipedia.org/wiki/JMP_(x86_instruction) http://en.wikipedia.org/wiki/NOP http://en.wikipedia.org/wiki/NOP http://en.wikipedia.org/wiki/Orthogonal#Computer_science http://en.wikipedia.org/wiki/Orthogonal#Computer_science http://en.wikipedia.org/wiki/Address_space http://en.wikipedia.org/wiki/Address_space http://en.wikipedia.org/wiki/Memory-mapped_I/O http://en.wikipedia.org/wiki/Memory-mapped_I/O http://en.wikipedia.org/wiki/Interrupt http://en.wikipedia.org/wiki/Interrupt And no, don't expect Python anytime soon. Expect a C compiler, FORTH, possibly some sort of Pascal, but a highly dynamic language is unlikely. The system is too resource-constrained to make it practical. A static language that looks kind of like Python isn't out of the question, but it won't do a lot of the things you expect from Python, Ruby, PHP, or Perl.
- SoftwarePatent 15y agoReading all these wikipedia pages is going to kill at least an hour of productivity today :/
- SimHacker 15y agoAnd it will enable countless years of productivity!
- 15y ago
- stusmith1977 15y ago> Explicit access to PC as a register, makes "computed goto" trivial and very natural. Am I right in thinking ARM uses this model? I haven't worked on them since ARM2, but I have a hazy recollection...
- dasmoth 15y agoYes it does. (Thinks of a typical SWI handler...)
- Symmetry 15y agoSort of. R15 is the PC, but you also have branch instructions which have very large literal values which in practice you'll always use. http://www.wss.co.uk/pinknoise/ARMinstrs/ARMinstrs.html#Branch http://www.wss.co.uk/pinknoise/ARMinstrs/ARMinstrs.html#Bran...
- keenerd 15y ago> No instructions for bit-manipulation. What? Plenty of opcodes for that. SHL, SHR, AND, BOR, XOR are all bitwise operators. Unless you mean bitset and bitclear macros, but no self respecting embedded programmer uses those. I've disagreed with almost everything else Notch has done, but from a simple pedagogical standpoint, he's doing the right thing by leaving those out.
- jimktrains2 15y agoWhy do you disagree? I've only been following this casually and don't now too much about the depths of what's going on.
- unwind 15y agoYeah, that was I meant, and they certainly don't have to be "macros", they can be full-blown instructions. Considering that even ARM's smaller "Thumb" instruction set has a bunch of them, I doubt that they're never used. Or, of course, they're just used by embedded compilers. :)
- aidenn0 15y agoNo rlwinm
- sp332 15y ago> No I/O instructions means I/O must be memory-mapped, further reducing the space available for code. In a tweet, notch said It's going to be dynamic later on, but right now [the keyboard is] a cyclic 16 letter buffer at 0x9000. 0=no char yet. Set to 0 after read. http://pastebin.com/raw.php?i=aJSkRMyC http://pastebin.com/raw.php?i=aJSkRMyC
- dspillett 15y agoThe thing that looked odd to me was: >* IFE, IFN, IFG, IFB take 2 cycles, plus the cost of a and b, plus 1 if the test fails* It is a long time since I worked in assembly, but I don't remember comparison functions having different timings depending on results when I were a lad. (FYI, most of the assembler I played with was for 6502s (in the old beebs) with a little for the Z80 family and early x86)
- msarnoff 15y agoAVR behaves similarly. Branch instructions take 1 cycle if the condition is false, and 2 if the condition is true.
- omgtehlion 15y agolow and mid-range PICs too
- AnIrishDuck 15y agoMany CPUs with branch prediction carry a penalty of a least one cycle for mispredicted branches as the fetch stage(s) of the pipeline must be invalidated. From wikipedia: The time that is wasted in case of a branch misprediction is equal to the number of stages in the pipeline from the fetch stage to the execute stage. Modern microprocessors tend to have quite long pipelines so that the misprediction delay is between 10 and 20 clock cycles. The longer the pipeline the higher the need for a good branch predictor. http://en.wikipedia.org/wiki/Branch_predictor http://en.wikipedia.org/wiki/Branch_predictor EDIT: the inclusion of this is somewhat interesting as there's not much of a point in simulating a pipelined processor unless you care about hardware details. My best guess is they're adding this "feature" to make compilation to assembly MORE difficult and increase the advantages of hand-compiled assembly. Branch prediction is a tricky thing to do right in compilers.
- dspillett 15y agoAh, obviously my experience is somewhat out of date! My "hacking cycles off loops in assembler" days were all before I got my hands on any kit advanced enough for pipelining and branch prediction to be a consideration.
- stephencanon 15y agoAsk and ye shall receive: http://stackoverflow.com/questions/10012522/are-the-i-and-j-registers-special-in-dcpu-16 http://stackoverflow.com/questions/10012522/are-the-i-and-j-...
- zoul 15y agohttp://stackoverflow.com/questions/tagged/dcpu-16 http://stackoverflow.com/questions/tagged/dcpu-16
- tptacek 15y agoThe DEC Alpha didn't have byte addressing either.