> During execution the registers allocated to a thread are private to it, i.e., other threads cannot read/write those registers. Wave intrinsics in HLSL, and s

> During execution the registers allocated to a thread are private to it, i.e., other threads cannot read/write those registers. Wave intrinsics in HLSL, and similar CUDA things can read registers from different threads within the current wavefront. Also, in the paragraph about memory architecture, I would mention the caches provide no coherency guarantees across threads of the same dispatch/grid, but there’s a special functional block global to the complete chips which implements atomics on global memory.