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Why was POWER9 open? https://www.devever.net/~hl/backstage-cast https://www.devever.net/~hl/backstage-cast > For Intel and AMD, the demarcation point between t

Why was POWER9 open? https://www.devever.net/~hl/backstage-cast https://www.devever.net/~hl/backstage-cast > For Intel and AMD, the demarcation point between them and their customer is the CPU, so if they want to keep secrets and maintain a stable interface between them and their customers, they're effectively pushed to do it at the CPU boundary. With IBM, this historically hasn't been the case; traditionally, IBM has only sold servers containing their own CPUs, not the CPUs alone. This means that traditionally, the only customer for IBM CPUs has been IBM — which means there's far less motivation for IBM to lock things down. Moreover, IBM Power servers have traditionally shipped with a proprietary hypervisor (known as PowerVM) built into the firmware. On these servers, all OSes run under this hypervisor, and you can't run an OS directly on the bare metal. This means that the natural interface between IBM and its customers has naturally fallen at the hypervisor—OS interface, not at the CPU.. > When IBM suddenly decided to open up their POWER CPUs for use by third parties, they made available a platform which for its entire lifespan up until that point, hadn't evolved under the same pressures as the existing x86 CPU market, but instead in an environment in which there was really no natural motive for them to lock things down at the CPU level. Which is almost certainly why IBM POWER CPUs seem to so greatly lack any “curtains” — the curtain had always been shipped with the hypervisor, not the CPU. HN discussion (2023): https://news.ycombinator.com/item?id=36127543 https://news.ycombinator.com/item?id=36127543 Why did POWER10 become less open, requiring binary blobs?

ksec 3y ago
>Why did POWER10 become less open, requiring binary blobs? Well the article did actually state it: avoiding Power10's notorious binary firmware requirement for OMI RAM and I/O. It is the requirement for OMI RAM and I/O. Not the CPU itself.
deleted 3y ago
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hamandcheese 3y ago
> they made available a platform which for its entire lifespan up until that point, hadn't evolved under the same pressures as the existing x86 CPU market, but instead in an environment in which there was really no natural motive for them to lock things down at the CPU level. What is the natural motivation for x86 manufactures to lock their CPUs down?
- smolder 3y ago
  There are several motivations for locking down x86. One of the biggest ones was DRM, the protected audio video path. The management engine on Intel also hosts TPM functionality, does some stuff with temperature sensing and fan control, and allows for some remote management. Those are all functions that Intel doesn't want end users or their installed software to be able to tamper with.
  - chasil 3y ago
    The "management engine" is a separate low-power CPU that is able to receive commands when the main power is off. This is used for off-hours patching and provisioning of corporate fleets. The CPU had previously been an ARC RISC core, but converted to an 80486 a few generations ago. The ME has had some showstopper bugs. https://en.m.wikipedia.org/wiki/Intel_Management_Engine https://en.m.wikipedia.org/wiki/Intel_Management_Engine
    - smolder 3y ago
      Yes, all that is true, and AMD has their PSP. ME and PSP represent the "locked-down" part of the x86 platform, running binary blobs that only the CPU makers have the capability to modify (in the absense of exploits.) Not unlike the binary blobs that led Raptor to use an alternative to IBM POWER10.
hlandau 3y ago
My understanding is that COVID happened and schedules slipped, and as a result they decided to licence some IP blocks from Synopsys (like a DDR4/5 PHY and a PCIe 5.0 PHY). Synopsys likes including control MCUs in their IP (yes, their DDR PHY has a MCU in it) which are intended to run a binary blob provided by them, and for which they will not give you the source code. For those curious, it's the same DDR PHY blob needed for memory bringup used by the i.MX8M and products based on it (e.g. Librem 5). Basically IBM facing delays chose to use the IP of Synopsys rather than make their own DDR5 and PCIe5 IP as they usually would (the fact they traditionally made all their own stuff is one of the reasons they were in the position to open 100% of the firmware of POWER9 in the first place), and dropped the ball on making sure that would meet the 100% open source firmware requirements of Raptor's customers. IBM walled themself into a corner here, as they're now dependent on Synopsys IP and it's not like they can persuade Synopsys to open their ahem precious IP. See my article (it was a hypothetical but has now been confirmed): https://www.devever.net/~hl/omi https://www.devever.net/~hl/omi (Of course the DDR PHY is on the OMI chip not the CPU, but with only one supplier of the required OMI chips this is a moot point. The PCIe5 PHY is on the CPU though and also needs a blob.)
- transpute 3y ago
  Thanks, super helpful comment & blog posts.

ksec 3y ago

>Why did POWER10 become less open, requiring binary blobs? Well the article did actually state it: avoiding Power10's notorious binary firmware requirement for OMI RAM and I/O. It is the requirement for OMI RAM and I/O. Not the CPU itself.

deleted 3y ago

[deleted]

hamandcheese 3y ago

> they made available a platform which for its entire lifespan up until that point, hadn't evolved under the same pressures as the existing x86 CPU market, but instead in an environment in which there was really no natural motive for them to lock things down at the CPU level. What is the natural motivation for x86 manufactures to lock their CPUs down?

smolder 3y ago
There are several motivations for locking down x86. One of the biggest ones was DRM, the protected audio video path. The management engine on Intel also hosts TPM functionality, does some stuff with temperature sensing and fan control, and allows for some remote management. Those are all functions that Intel doesn't want end users or their installed software to be able to tamper with.
- chasil 3y ago
  The "management engine" is a separate low-power CPU that is able to receive commands when the main power is off. This is used for off-hours patching and provisioning of corporate fleets. The CPU had previously been an ARC RISC core, but converted to an 80486 a few generations ago. The ME has had some showstopper bugs. https://en.m.wikipedia.org/wiki/Intel_Management_Engine https://en.m.wikipedia.org/wiki/Intel_Management_Engine
  - smolder 3y ago
    Yes, all that is true, and AMD has their PSP. ME and PSP represent the "locked-down" part of the x86 platform, running binary blobs that only the CPU makers have the capability to modify (in the absense of exploits.) Not unlike the binary blobs that led Raptor to use an alternative to IBM POWER10.

hlandau 3y ago

My understanding is that COVID happened and schedules slipped, and as a result they decided to licence some IP blocks from Synopsys (like a DDR4/5 PHY and a PCIe 5.0 PHY). Synopsys likes including control MCUs in their IP (yes, their DDR PHY has a MCU in it) which are intended to run a binary blob provided by them, and for which they will not give you the source code. For those curious, it's the same DDR PHY blob needed for memory bringup used by the i.MX8M and products based on it (e.g. Librem 5). Basically IBM facing delays chose to use the IP of Synopsys rather than make their own DDR5 and PCIe5 IP as they usually would (the fact they traditionally made all their own stuff is one of the reasons they were in the position to open 100% of the firmware of POWER9 in the first place), and dropped the ball on making sure that would meet the 100% open source firmware requirements of Raptor's customers. IBM walled themself into a corner here, as they're now dependent on Synopsys IP and it's not like they can persuade Synopsys to open their ahem precious IP. See my article (it was a hypothetical but has now been confirmed): https://www.devever.net/~hl/omi https://www.devever.net/~hl/omi (Of course the DDR PHY is on the OMI chip not the CPU, but with only one supplier of the required OMI chips this is a moot point. The PCIe5 PHY is on the CPU though and also needs a blob.)

transpute 3y ago
Thanks, super helpful comment & blog posts.