6 ms·

> I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bi

by tw1984 3y ago

> I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. because it is a design that belong to yesterday, initially built by people who came from a completely different age & era. why bother fixing/improving a failed design when there are widely adopted successful alternatives? > I thought that the UltraSPARC T1/Niagara was a really amazing concept T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? > if maybe a few years too early or maybe it is a totally failed product that shouldn't be designed in the first place. > I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? maybe because people don't want to be the victim of T1's fraud again? honestly, you are kidding yourself if you consider T1 as something amazing. For me, it was a heart breaking experience once the horrible floating point performance was verified. > so there was time to adopt them as well. again, people don't want to be the victim of the T1 floating point performance drama. you hit people hard once, they see your true potential and walk away, that is not very hard to understand, right?

jfim 3y ago
> T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? It was designed for the heavily parallel web workloads of the 2000s, which don't use floating point, hence the multiple threads per FPU.
- tw1984 3y ago
  > It was designed for the heavily parallel web workloads of the 2000s No. According to its official datasheet, "this processor targets commercial applications such as application servers and database servers". I thought floating point is an essential part of databases. That being said, given it is a fraud from the beginning, I can accept the fact that the official T1 datasheet is intentionally misleading its potential buyers. > which don't use floating point, hence the multiple threads per FPU. are you implying that it was mistake to implement more FPUs in their subsequent T2? there are certain shortcuts you don't make in engineering. when building an generic processor aiming to take on the application & database servers, you don't stupidly have a single FPU for the entire processor when letting your big mouth PR department talking about how great is the throughput.
  - jfim 3y ago
    > I thought floating point is an essential part of databases. Have you ever implemented a database? Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.
    - tw1984 3y ago
      > Have you ever implemented a database? Yes, multiple times, in both American companies and in Chinese startups. > Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That is not a justification for having only one FPU. Let's use logic here, it is not that hard. > That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. Again, that doesn't justify the stupidity of having just one FPU. > It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments. I am now totally confused. You are defending the stupid T1 design which only has 1 FPU for its entire processor capable of running 32 threads in parallel, yet your argument is that such design is meant for multi-threaded workloads? I thought you need multiple FPUs to truly parallelize those multi-threaded workloads.
      - aleph_minus_one 3y ago
        As jfim wrote (emphasis mine): "It was designed for the heavily parallel web workloads of the 2000s". At this time, this mostly meant integer workload. For todays's workloads even in this particular domain, having only one FPU for 32 threads is likely a bad idea, but at that time, this was a perfectly acceptable compromise for this kind of application. These were simply different times.
  - deaddodo 3y ago
inkyoto 3y ago
> because it is a design that belong to yesterday Which parts of the POWER architecture design belong to yesterday? Specific examples would be great.
- tw1984 3y ago
  the so called POWER architecture covers like 35 years of development, the latest iteration probably implements some of the latest stuff in the area as it is an experimental platform for researchers. it is still a design of yesterday because you don't get access to tier 1 software ecosystem. it is a modernized VAX for hobbyists.
  - ksec 3y ago
    What? So what is your definition of Modern architecture ? I am assuming you are referring to ISA here.
    - tw1984 3y ago
      AMD64, ARM64, RISC-V. This is not rocket science. No one needs POWER. Museum is a better place for those kind of vintage stuff.
      - ksec 3y ago
        >AMD64, ARM64, RISC-V. This is not rocket science. You should re-read what you wrote. [1], and I will leave that as it is. And contrary to what you have been finger pointing. And no one is getting emotional. [1]. the so called POWER architecture covers like 35 years of development,
  - inkyoto 3y ago
    Still no specific examples, just handwaving? SPARC, Intel i960, AMD29k, ARM, RISC-V and many others are direct descendants of the Berkeley RISC design. Using the number of years of a measure of technological relevance, it can be argued that ARM and RISC-V designs are even older than 35 years. It is pure sophism, though, and it does not help. By the same token, all modern computing architectures are fossilised designs because they are based on the von Neumann architecture from 1945.
rbanffy 3y ago
> because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? How would ARM and x86 be "open"?
shrubble 3y ago
The T2 fixed what you are complaining about. Was released in 2007.
- tw1984 3y ago
  The same year when SUN decided to use processors from both AMD and Intel to replace its own.
  - shrubble 3y ago
    Seeing as they kept making SPARC CPUs for a decade longer, not really. 'Show me on the 1U chassis where the bad CPU touched you' is the vibe I'm getting from your comments in this thread.
    - helf 3y ago
      [dead]
    - tw1984 3y ago
      > Seeing as they kept making SPARC CPUs for a decade longer because there were poor customers stuck in the SPARC trap. it would them huge to move to a different ISA and there is usually no $ return for doing that. trying not to further damage its PR, they thus decided to keep the production going. same logic for Intel making Itanium all the way until 2018 or 2019.

by tw1984 3y ago

jfim 3y ago

> T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? It was designed for the heavily parallel web workloads of the 2000s, which don't use floating point, hence the multiple threads per FPU.

tw1984 3y ago
> It was designed for the heavily parallel web workloads of the 2000s No. According to its official datasheet, "this processor targets commercial applications such as application servers and database servers". I thought floating point is an essential part of databases. That being said, given it is a fraud from the beginning, I can accept the fact that the official T1 datasheet is intentionally misleading its potential buyers. > which don't use floating point, hence the multiple threads per FPU. are you implying that it was mistake to implement more FPUs in their subsequent T2? there are certain shortcuts you don't make in engineering. when building an generic processor aiming to take on the application & database servers, you don't stupidly have a single FPU for the entire processor when letting your big mouth PR department talking about how great is the throughput.
- jfim 3y ago
  > I thought floating point is an essential part of databases. Have you ever implemented a database? Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.
  - tw1984 3y ago
    > Have you ever implemented a database? Yes, multiple times, in both American companies and in Chinese startups. > Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That is not a justification for having only one FPU. Let's use logic here, it is not that hard. > That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. Again, that doesn't justify the stupidity of having just one FPU. > It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments. I am now totally confused. You are defending the stupid T1 design which only has 1 FPU for its entire processor capable of running 32 threads in parallel, yet your argument is that such design is meant for multi-threaded workloads? I thought you need multiple FPUs to truly parallelize those multi-threaded workloads.
    - aleph_minus_one 3y ago
      As jfim wrote (emphasis mine): "It was designed for the heavily parallel web workloads of the 2000s". At this time, this mostly meant integer workload. For todays's workloads even in this particular domain, having only one FPU for 32 threads is likely a bad idea, but at that time, this was a perfectly acceptable compromise for this kind of application. These were simply different times.
- deaddodo 3y ago

inkyoto 3y ago

> because it is a design that belong to yesterday Which parts of the POWER architecture design belong to yesterday? Specific examples would be great.

tw1984 3y ago
the so called POWER architecture covers like 35 years of development, the latest iteration probably implements some of the latest stuff in the area as it is an experimental platform for researchers. it is still a design of yesterday because you don't get access to tier 1 software ecosystem. it is a modernized VAX for hobbyists.
- ksec 3y ago
  What? So what is your definition of Modern architecture ? I am assuming you are referring to ISA here.
  - tw1984 3y ago
    AMD64, ARM64, RISC-V. This is not rocket science. No one needs POWER. Museum is a better place for those kind of vintage stuff.
    - ksec 3y ago
      >AMD64, ARM64, RISC-V. This is not rocket science. You should re-read what you wrote. [1], and I will leave that as it is. And contrary to what you have been finger pointing. And no one is getting emotional. [1]. the so called POWER architecture covers like 35 years of development,
- inkyoto 3y ago
  Still no specific examples, just handwaving? SPARC, Intel i960, AMD29k, ARM, RISC-V and many others are direct descendants of the Berkeley RISC design. Using the number of years of a measure of technological relevance, it can be argued that ARM and RISC-V designs are even older than 35 years. It is pure sophism, though, and it does not help. By the same token, all modern computing architectures are fossilised designs because they are based on the von Neumann architecture from 1945.

rbanffy 3y ago

> because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? How would ARM and x86 be "open"?

shrubble 3y ago

The T2 fixed what you are complaining about. Was released in 2007.

tw1984 3y ago
The same year when SUN decided to use processors from both AMD and Intel to replace its own.
- shrubble 3y ago
  Seeing as they kept making SPARC CPUs for a decade longer, not really. 'Show me on the 1U chassis where the bad CPU touched you' is the vibe I'm getting from your comments in this thread.
  - helf 3y ago
    [dead]
  - tw1984 3y ago
    > Seeing as they kept making SPARC CPUs for a decade longer because there were poor customers stuck in the SPARC trap. it would them huge to move to a different ISA and there is usually no $ return for doing that. trying not to further damage its PR, they thus decided to keep the production going. same logic for Intel making Itanium all the way until 2018 or 2019.