9 ms·

Okay, I know I'm "that guy" that just has to bring RISC-V into any discussion: Why hasn't there been more adoption/movement of OpenPOWER or OpenSPARC? I assume

Okay, I know I'm "that guy" that just has to bring RISC-V into any discussion: Why hasn't there been more adoption/movement of OpenPOWER or OpenSPARC? I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. I thought that the UltraSPARC T1/Niagara was a really amazing concept, if maybe a few years too early (and definitely in the wrong hands after Sun was extinguished), so I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch - especially one that seems more suited for ultra-low power microcontrollers. OpenPOWER was founded 10 years ago, OpenSPARC is even older, the T1 code was released in 2006 - so there was time to adopt them as well. Is the existing ISA too hard to get into lower power chips? Are there any weird patent/licensing issues going on that don't make them as "Open"? Could I please get a modern, high-end SPARC workstation?

orbifold 3y ago
Have looked at the T1 Code? It far from obvious how you would use that as a starting point for a new chip. You need a lot of expertise for custom memory blocks etc. and there aren’t any tests included if I remember correctly.
- MenhirMike 3y ago
  No, I'm on the software side of things, so I mainly see what compilers/toolchains I have to work with and what performance I get, but no idea about the nitty gritty of chip design apart from from surface knowledge.
tw1984 3y ago
> I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. because it is a design that belong to yesterday, initially built by people who came from a completely different age & era. why bother fixing/improving a failed design when there are widely adopted successful alternatives? > I thought that the UltraSPARC T1/Niagara was a really amazing concept T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? > if maybe a few years too early or maybe it is a totally failed product that shouldn't be designed in the first place. > I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? maybe because people don't want to be the victim of T1's fraud again? honestly, you are kidding yourself if you consider T1 as something amazing. For me, it was a heart breaking experience once the horrible floating point performance was verified. > so there was time to adopt them as well. again, people don't want to be the victim of the T1 floating point performance drama. you hit people hard once, they see your true potential and walk away, that is not very hard to understand, right?
- jfim 3y ago
  > T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? It was designed for the heavily parallel web workloads of the 2000s, which don't use floating point, hence the multiple threads per FPU.
  - tw1984 3y ago
    > It was designed for the heavily parallel web workloads of the 2000s No. According to its official datasheet, "this processor targets commercial applications such as application servers and database servers". I thought floating point is an essential part of databases. That being said, given it is a fraud from the beginning, I can accept the fact that the official T1 datasheet is intentionally misleading its potential buyers. > which don't use floating point, hence the multiple threads per FPU. are you implying that it was mistake to implement more FPUs in their subsequent T2? there are certain shortcuts you don't make in engineering. when building an generic processor aiming to take on the application & database servers, you don't stupidly have a single FPU for the entire processor when letting your big mouth PR department talking about how great is the throughput.
    - jfim 3y ago
      > I thought floating point is an essential part of databases. Have you ever implemented a database? Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.
      - tw1984 3y ago
        > Have you ever implemented a database? Yes, multiple times, in both American companies and in Chinese startups. > Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That is not a justification for having only one FPU. Let's use logic here, it is not that hard. > That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. Again, that doesn't justify the stupidity of having just one FPU. > It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments. I am now totally confused. You are defending the stupid T1 design which only has 1 FPU for its entire processor capable of running 32 threads in parallel, yet your argument is that such design is meant for multi-threaded workloads? I thought you need multiple FPUs to truly parallelize those multi-threaded workloads.
raverbashing 3y ago
Isn't the SPARC ISA super annoying to work with, with 'register windows' and other things that don't make sense in the current year?
- nubinetwork 3y ago
  SPARC, PPC, and ARM can all run Linux just fine.
  - raverbashing 3y ago
    Yes but why would you waste silicon implementing complicated stuff from the 90s when you can have something more modern like RISCV or ARM?
    - guenthert 3y ago
      I'm confused about what is called modern here and why. In any case I (and I am sure the vast majority) of consumers and application developers (system developers are of course in a different position) doesn't care one bit about the inner workings until some inherent security flaw like SPECTRE arises.
    - inkyoto 3y ago
      Register windows and register files are the same thing. Most RISC architectures have eschewed the register windows in favour of the register files coupled with the register renaming though. Silicon is «wasted» (debatable) in high-performance CPU designs employing the register files but can be saved in low-cost designs by not implementing a register file at the performance penalty cost. Same is true for the designs with register windows. The difference between the two is that with the register window the onus of tracking the dependencies in the data flow in registers is explicitly on the compiler (or on the developer) whereas with the register file the onus is on the CPU to track the dependencies, apply heuristics, allocate shadow registers from the register file, rename the in-use registers onto the shadow registers and vice versa. Modern high-performance CPU implementations that do not employ the register windows typically come with large or very large register files (100-300 circa registers are common).
RedShift1 3y ago
Goes to web site. Talos™ II Entry-Level Developer System TLSDS3. Nice, looks good. Starting at $5,818.99. Nope.
- nubinetwork 3y ago
  This, I would love to have some SPARC or PPC hardware, but it always comes down to price and power consumption (and noise because I'd probably be sleeping next to the thing)
  - classichasclass 3y ago
    Price is one thing, but the Talos 2 I'm typing this on is whisper-quiet. I only hear it when the fans spool up during a heavy compute job. Otherwise it's silent except for whatever case fans you choose to have.
    - nubinetwork 3y ago
      Don't get me wrong, my ARM stuff is quiet too, but if I wanted one of those dual-dual-core G5's from yesteryear, I'd need some earplugs. :)
      - classichasclass 3y ago
        I've got one of the Quad G5 Macs too, sitting right next to it (in fact, I upgraded from the Quad directly to the Talos 2). The Quad is also very quiet in idle, but you have to downclock it in System Preferences to be as silent as the T2 is in normal operation, and even with a well-maintained liquid cooling system the G5's roar at full tilt is loud (it's really loud if it's not). The high speed fans in the T2 are more like a quiet whine than what the G5 generates, let alone the wind tunnel MDD G4 I ran before that. And no LCS! And the G5 is doing that with four cores and four threads, while the Talos II is doing that with sixteen cores and 64 threads. Now, the Quad G5 also came out in 2005, and I got the T2 in 2018. But thirteen years later I'm happy to say that the noise level is absolutely no worse than any other modern workstation on x86_64.
snvzz 3y ago
>Why hasn't there been more adoption/movement of OpenPOWER or OpenSPARC? For the same reasons RISC-V had to be created. This is documented in the paper Instruction Sets Should Be Free: The Case For RISC-V[0]. 0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...
- MenhirMike 3y ago
  Ah, it explicitly calls out OpenPOWER: > Even “OpenPOWER” is an oxymoron; you must pay IBM to use its ISA. I guess that is also the issue with Power10 here that causes Raptor to go its own way. For SPARC, it mentions the 32-Bit SPARC v8 and says that 64-Bit SPARC v9 is proprietary, which seems weird given that the T1/T2 are based on that SPARC v9, but I guess that just because the CPU Core is licensed under GPL, the ISA itself is still encumbered? Anyway, that paper is a great read, thanks! It will have to be seen if this statement will age like milk or like fine wine: > RISC-V is also 10 to 20 years younger, so we had the chance to learn from and fix the mistakes of previous RISC ISAs In software, the desire to throw away all the old and start brand new is often a bad idea because a lot of the janky stuff in the old stuff exists for a reason, often not a very obvious one. But no idea how much baggage old ISAs carry that can be truly discarded, achieving high performance is often a messy affair.
  - sillywalk 3y ago
    > I guess that is also the issue with Power10 here that causes Raptor to go its own way. I thought avoiding the POWER10 was the result of firmware blobs. [0][1] "While we applaud the overall extent of source code available for the #POWER10 firmware stack, two key P10-specific firmware components remain closed source at this time. The first is the off-chip OMI DRAM bridge, and the second is the on-chip PPE I/O processor" [2] [0] https://www.devever.net/~hl/omi https://www.devever.net/~hl/omi [1] https://www.talospace.com/2021/09/its-not-just-omi-thats-trouble-with.html https://www.talospace.com/2021/09/its-not-just-omi-thats-tro... [2] https://twitter.com/RaptorCompSys/status/1435510763402244105 https://twitter.com/RaptorCompSys/status/1435510763402244105

orbifold 3y ago

Have looked at the T1 Code? It far from obvious how you would use that as a starting point for a new chip. You need a lot of expertise for custom memory blocks etc. and there aren’t any tests included if I remember correctly.

MenhirMike 3y ago
No, I'm on the software side of things, so I mainly see what compilers/toolchains I have to work with and what performance I get, but no idea about the nitty gritty of chip design apart from from surface knowledge.

tw1984 3y ago

> I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. because it is a design that belong to yesterday, initially built by people who came from a completely different age & era. why bother fixing/improving a failed design when there are widely adopted successful alternatives? > I thought that the UltraSPARC T1/Niagara was a really amazing concept T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? > if maybe a few years too early or maybe it is a totally failed product that shouldn't be designed in the first place. > I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? maybe because people don't want to be the victim of T1's fraud again? honestly, you are kidding yourself if you consider T1 as something amazing. For me, it was a heart breaking experience once the horrible floating point performance was verified. > so there was time to adopt them as well. again, people don't want to be the victim of the T1 floating point performance drama. you hit people hard once, they see your true potential and walk away, that is not very hard to understand, right?

jfim 3y ago
> T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? It was designed for the heavily parallel web workloads of the 2000s, which don't use floating point, hence the multiple threads per FPU.
- tw1984 3y ago
  > It was designed for the heavily parallel web workloads of the 2000s No. According to its official datasheet, "this processor targets commercial applications such as application servers and database servers". I thought floating point is an essential part of databases. That being said, given it is a fraud from the beginning, I can accept the fact that the official T1 datasheet is intentionally misleading its potential buyers. > which don't use floating point, hence the multiple threads per FPU. are you implying that it was mistake to implement more FPUs in their subsequent T2? there are certain shortcuts you don't make in engineering. when building an generic processor aiming to take on the application & database servers, you don't stupidly have a single FPU for the entire processor when letting your big mouth PR department talking about how great is the throughput.
  - jfim 3y ago
    > I thought floating point is an essential part of databases. Have you ever implemented a database? Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.
    - tw1984 3y ago
      > Have you ever implemented a database? Yes, multiple times, in both American companies and in Chinese startups. > Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data. That is not a justification for having only one FPU. Let's use logic here, it is not that hard. > That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses. Again, that doesn't justify the stupidity of having just one FPU. > It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments. I am now totally confused. You are defending the stupid T1 design which only has 1 FPU for its entire processor capable of running 32 threads in parallel, yet your argument is that such design is meant for multi-threaded workloads? I thought you need multiple FPUs to truly parallelize those multi-threaded workloads.

raverbashing 3y ago

Isn't the SPARC ISA super annoying to work with, with 'register windows' and other things that don't make sense in the current year?

nubinetwork 3y ago
SPARC, PPC, and ARM can all run Linux just fine.
- raverbashing 3y ago
  Yes but why would you waste silicon implementing complicated stuff from the 90s when you can have something more modern like RISCV or ARM?
  - guenthert 3y ago
    I'm confused about what is called modern here and why. In any case I (and I am sure the vast majority) of consumers and application developers (system developers are of course in a different position) doesn't care one bit about the inner workings until some inherent security flaw like SPECTRE arises.
  - inkyoto 3y ago
    Register windows and register files are the same thing. Most RISC architectures have eschewed the register windows in favour of the register files coupled with the register renaming though. Silicon is «wasted» (debatable) in high-performance CPU designs employing the register files but can be saved in low-cost designs by not implementing a register file at the performance penalty cost. Same is true for the designs with register windows. The difference between the two is that with the register window the onus of tracking the dependencies in the data flow in registers is explicitly on the compiler (or on the developer) whereas with the register file the onus is on the CPU to track the dependencies, apply heuristics, allocate shadow registers from the register file, rename the in-use registers onto the shadow registers and vice versa. Modern high-performance CPU implementations that do not employ the register windows typically come with large or very large register files (100-300 circa registers are common).

RedShift1 3y ago

Goes to web site. Talos™ II Entry-Level Developer System TLSDS3. Nice, looks good. Starting at $5,818.99. Nope.

nubinetwork 3y ago
This, I would love to have some SPARC or PPC hardware, but it always comes down to price and power consumption (and noise because I'd probably be sleeping next to the thing)
- classichasclass 3y ago
  Price is one thing, but the Talos 2 I'm typing this on is whisper-quiet. I only hear it when the fans spool up during a heavy compute job. Otherwise it's silent except for whatever case fans you choose to have.
  - nubinetwork 3y ago
    Don't get me wrong, my ARM stuff is quiet too, but if I wanted one of those dual-dual-core G5's from yesteryear, I'd need some earplugs. :)
    - classichasclass 3y ago
      I've got one of the Quad G5 Macs too, sitting right next to it (in fact, I upgraded from the Quad directly to the Talos 2). The Quad is also very quiet in idle, but you have to downclock it in System Preferences to be as silent as the T2 is in normal operation, and even with a well-maintained liquid cooling system the G5's roar at full tilt is loud (it's really loud if it's not). The high speed fans in the T2 are more like a quiet whine than what the G5 generates, let alone the wind tunnel MDD G4 I ran before that. And no LCS! And the G5 is doing that with four cores and four threads, while the Talos II is doing that with sixteen cores and 64 threads. Now, the Quad G5 also came out in 2005, and I got the T2 in 2018. But thirteen years later I'm happy to say that the noise level is absolutely no worse than any other modern workstation on x86_64.

snvzz 3y ago

>Why hasn't there been more adoption/movement of OpenPOWER or OpenSPARC? For the same reasons RISC-V had to be created. This is documented in the paper Instruction Sets Should Be Free: The Case For RISC-V[0]. 0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...

MenhirMike 3y ago
Ah, it explicitly calls out OpenPOWER: > Even “OpenPOWER” is an oxymoron; you must pay IBM to use its ISA. I guess that is also the issue with Power10 here that causes Raptor to go its own way. For SPARC, it mentions the 32-Bit SPARC v8 and says that 64-Bit SPARC v9 is proprietary, which seems weird given that the T1/T2 are based on that SPARC v9, but I guess that just because the CPU Core is licensed under GPL, the ISA itself is still encumbered? Anyway, that paper is a great read, thanks! It will have to be seen if this statement will age like milk or like fine wine: > RISC-V is also 10 to 20 years younger, so we had the chance to learn from and fix the mistakes of previous RISC ISAs In software, the desire to throw away all the old and start brand new is often a bad idea because a lot of the janky stuff in the old stuff exists for a reason, often not a very obvious one. But no idea how much baggage old ISAs carry that can be truly discarded, achieving high performance is often a messy affair.
- sillywalk 3y ago
  > I guess that is also the issue with Power10 here that causes Raptor to go its own way. I thought avoiding the POWER10 was the result of firmware blobs. [0][1] "While we applaud the overall extent of source code available for the #POWER10 firmware stack, two key P10-specific firmware components remain closed source at this time. The first is the off-chip OMI DRAM bridge, and the second is the on-chip PPE I/O processor" [2] [0] https://www.devever.net/~hl/omi https://www.devever.net/~hl/omi [1] https://www.talospace.com/2021/09/its-not-just-omi-thats-trouble-with.html https://www.talospace.com/2021/09/its-not-just-omi-thats-tro... [2] https://twitter.com/RaptorCompSys/status/1435510763402244105 https://twitter.com/RaptorCompSys/status/1435510763402244105