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The next Raptor OpenPOWER systems are coming, but they won't be Power10
- wmf 3y agoThis is extremely suspicious. A totally unknown company is making a high-performance PowerPC processor? Why?
- ikmckenz 3y agoBecause they still sell like hotcakes even with the crazy price tag.
- radicaldreamer 3y agoWhy though? Is there something about the instruction set that is much faster for some kinds of processing (altivec?) or people just need to run old software thats hard to rewrite?
- rus20376 3y agoAt least part of the reason is not technical, but philosophical. See the third item in the FAQ https://secure.raptorcs.com/content/base/faq.html https://secure.raptorcs.com/content/base/faq.html These CPUs are completely open and "free". In addition to the libre philosophy this guarantees a level of security unobtainable with any other CPU. The same rationale is behind the powerpc laptop project https://www.powerpc-notebook.org/en/ https://www.powerpc-notebook.org/en/
- pram 3y agoYes a lot of stuff historically that was built with IBM XL for AIX. A lot of Fortran software, a lot of bank related shit. This kind of stuff is simultaneously extremely critical and also just cruising on intertia.
- wmf 3y agoNobody runs that software on Raptor though.
- numpad0 3y agoMaybe military? There were always $10-20k laptops in near-nonsensical architectures like POWER5, UltraSPARC, dual socket Pentium 4, and such. Maybe they run military radar tools and/or "gas/oil" workloads. Maybe it makes sense for somebody.
- RedShift1 3y agoDual socket pentium 4? I don't think that existed. Dual xeon sure, lots of those.
- OmarAssadi 3y agoI haven't found a system with multiple Pentium 4s (but I think NetBurst Xeons were literally pretty much Pentium 4s without disabled SMP?). That said, who knows, I almost wouldn't be surprised; there's been loads of weird unique systems. Compaq SystemPro had custom SMP support to allow for dual 386s, which IIRC is even supported by Windows NT 3.1 officially. I think IBM x445s had some custom crazy interconnect for 32-way Xeon MPs, etc.
- the-dude 3y agoSure they did, the AsRock P4 Combo for example ( didn't find any in laptop form-factor though ).
- RedShift1 3y agoYou can't use both CPUs at the same time with that one. If you install both either something will explode, nothing will happen, or it'll just use one of them (probably configured using a jumper)
- the-dude 3y agoAh, oh. I suppose you are right. I just pulled that one out of zhe Google because I remember having a dual socket P4 motherboard, with just one CPU fitted though. This was in 2001, maybe I am misremembering and it was P3?
- MenhirMike 3y agoRaptor has been making POWER-based machines for quite a few years now. Their Talos line was one of the first systems to have PCI Express 4.0 back in the day: https://www.phoronix.com/news/Talos-2-Initial-Hands-On https://www.phoronix.com/news/Talos-2-Initial-Hands-On (EDIT: OP was talking about the chip manufacturer, not the system maker. And OP is asking a very good question.)
- wmf 3y agoThe chip isn't from Raptor; it's from Solid Silicon. Why does Solid Silicon exist?
- MenhirMike 3y agoAh, now THAT is a good and interesting question. I know that there's been a lot of funding for Texas chip fabs, but yeah, no idea who those guys are. (Edit: According to their website, they're fabless. So that's even weirder. And I'm surprised that one can trademark the paragraph symbol(§) like they claim to have done.)
- jabl 3y agoWell, the fabless part is at least easy to understand. Building a new high end fab costs billions and requires deep expertise that takes years, if not decades, to build. Practically every chip company these days is fabless. Intel is the exception, not the rule. That being said, designing a new high end cpu is very expensive and complex. That a hitherto unknown company embarks on such a project is, indeed, very suspicious.
- formerly_proven 3y ago> Practically every chip company these days is fabless. Intel is the exception, not the rule. A lot of analog and mixed-signal companies aren't: TI, NXP, ADI (with LT, ON Semi, Maxim, ...), Avago/Broadcom, AMS, Bosch, Infineon, Elmos etc.; also "the Japanese" (Sony, Fujitsu, Oki, Canon, Rohm and probably more)
- Shekelphile 3y agoThe claim that these CPUs are 'cutting edge' despite being based on the older POWER9 uarch is dubious as well. I suspect this is simply a marketing sham and the CPUs talos continues to ship will be rebrands of their current offering. That said, if they have the original designs for these CPUs then it's not impossible for a startup to make meaningful improvements, but it almost certainly isn't going to be fabbed on a cutting edge node and certainly won't be competitive with anything else on the market (not that they were to begin with).
- ksec 3y ago>Raptor's newest systems are planned for late 2024. Damn it I got excited and then saw that line. But it is nice we have a new entry to OpenPOWER world. I could at least extend the POWER and FreeBSD combination for a little longer. I am also wondering who is the backer of Solid Silicon. As much as I love the idea, I would imagine it is a very hard sell to most VC. ( But then VC are known to invest in Cloud Kitchen and FTX saving the world so I guess I shouldn't be surprised )
- MenhirMike 3y agoOkay, I know I'm "that guy" that just has to bring RISC-V into any discussion: Why hasn't there been more adoption/movement of OpenPOWER or OpenSPARC? I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. I thought that the UltraSPARC T1/Niagara was a really amazing concept, if maybe a few years too early (and definitely in the wrong hands after Sun was extinguished), so I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch - especially one that seems more suited for ultra-low power microcontrollers. OpenPOWER was founded 10 years ago, OpenSPARC is even older, the T1 code was released in 2006 - so there was time to adopt them as well. Is the existing ISA too hard to get into lower power chips? Are there any weird patent/licensing issues going on that don't make them as "Open"? Could I please get a modern, high-end SPARC workstation?
- orbifold 3y agoHave looked at the T1 Code? It far from obvious how you would use that as a starting point for a new chip. You need a lot of expertise for custom memory blocks etc. and there aren’t any tests included if I remember correctly.
- MenhirMike 3y agoNo, I'm on the software side of things, so I mainly see what compilers/toolchains I have to work with and what performance I get, but no idea about the nitty gritty of chip design apart from from surface knowledge.
- tw1984 3y ago> I assume that they have extremely solid toolchains available, and the feature sets were obviously mature enough for high end computing, and they've been 64-Bit for a long time. because it is a design that belong to yesterday, initially built by people who came from a completely different age & era. why bother fixing/improving a failed design when there are widely adopted successful alternatives? > I thought that the UltraSPARC T1/Niagara was a really amazing concept T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point? > if maybe a few years too early or maybe it is a totally failed product that shouldn't be designed in the first place. > I'm just scratching my head why everyone's so gung-ho at starting a brand new architecture from scratch because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments? maybe because people don't want to be the victim of T1's fraud again? honestly, you are kidding yourself if you consider T1 as something amazing. For me, it was a heart breaking experience once the horrible floating point performance was verified. > so there was time to adopt them as well. again, people don't want to be the victim of the T1 floating point performance drama. you hit people hard once, they see your true potential and walk away, that is not very hard to understand, right?
- random3 3y agoCan someone provide some good context/resources on this?
- nvy 3y agoopenPOWER is IBM's attempt to make the Power architecture relevant. RaptorCS makes super dank but also super pricey desktop systems. Some new startup called Solid Silicon has partnered with another company called Lattice to make the chips in Raptor's next line of systems.
- bunnie 3y agoI can't seem to find any information on Solid Silicon, the company making the CPU. Anyone have a link or more details on this company? The website I can find for Solid Silicon [1] is delightfully devoid of details. [1] https://www.solidsilicon.com https://www.solidsilicon.com
- nvy 3y agoLooks like they're a new startup. Their previous product, the X1, was/is a collaboration with Lattice. Looks like this S1 will be another collab.
- broodbucket 3y agoWHOIS points to Raptor so I'd say it's themselves under a different name.
- classichasclass 3y ago(author) Raptor is probably just hosting them on their own cloud platform. My conversations with Raptor indicate it's a different company. I've got an inquiry out to chat with them and it's been passed along.
- aidenn0 3y agohttps://www.linkedin.com/company/solid-silicon?trk=public_post_feed-actor-name https://www.linkedin.com/company/solid-silicon?trk=public_po...
- transpute 3y agoHopefully the new ISA will continue to support tagged memory pointers (capability computing), which can stop many security attacks, https://www.talospace.com/2022/10/power9-and-tagged-memory-and-why-you.html https://www.talospace.com/2022/10/power9-and-tagged-memory-a... & https://www.devever.net/~hl/ppcas https://www.devever.net/~hl/ppcas > IBM's capability-based design is implemented using a hybrid of both hardware and software. The central premise of the design is that you cannot write native code for the platform directly; instead, all programs for the system must be written in an intermediate language which is translated internally (at installation time) to Power ISA machine code by the system's “kernel”. This trusted translator maintains the desired security invariants of the system, just like the modern sandboxed JIT designs used in Java, .NET, JavaScript and WebAssembly, and without relying on hardware memory protection. > In order to support this capability-based OS, IBM implemented an undocumented extension to the Power ISA known as PowerPC AS. This ISA extension provides a memory tagging system which associates one tag bit with every aligned 16 bytes of system memory (a quadword). In a 128-bit pointer, 64 bits are used for the typical memory address; the other half stores a few bits of metadata and is otherwise reserved (the degree of futureproofing is rather extreme). HN discussion (2022), https://news.ycombinator.com/item?id=33381823 https://news.ycombinator.com/item?id=33381823
- deleted 3y ago[deleted]
- sillywalk 3y agoIt's doubtful IBM would drop that support, the PowerPC AS set is required to run the 'i' a.k.a. OS/400 operating system. The original series of processors that implemented PowerPC AS were called RS64. IBM merged this with the POWER (RS/6000) series. All POWER processors since the POWER4 have the tagging instructions. It would be nice if IBM would document them, so Linux and/or AIX could use them.
- transpute 3y agoWhy was POWER9 open? https://www.devever.net/~hl/backstage-cast https://www.devever.net/~hl/backstage-cast > For Intel and AMD, the demarcation point between them and their customer is the CPU, so if they want to keep secrets and maintain a stable interface between them and their customers, they're effectively pushed to do it at the CPU boundary. With IBM, this historically hasn't been the case; traditionally, IBM has only sold servers containing their own CPUs, not the CPUs alone. This means that traditionally, the only customer for IBM CPUs has been IBM — which means there's far less motivation for IBM to lock things down. Moreover, IBM Power servers have traditionally shipped with a proprietary hypervisor (known as PowerVM) built into the firmware. On these servers, all OSes run under this hypervisor, and you can't run an OS directly on the bare metal. This means that the natural interface between IBM and its customers has naturally fallen at the hypervisor—OS interface, not at the CPU.. > When IBM suddenly decided to open up their POWER CPUs for use by third parties, they made available a platform which for its entire lifespan up until that point, hadn't evolved under the same pressures as the existing x86 CPU market, but instead in an environment in which there was really no natural motive for them to lock things down at the CPU level. Which is almost certainly why IBM POWER CPUs seem to so greatly lack any “curtains” — the curtain had always been shipped with the hypervisor, not the CPU. HN discussion (2023): https://news.ycombinator.com/item?id=36127543 https://news.ycombinator.com/item?id=36127543 Why did POWER10 become less open, requiring binary blobs?
- ksec 3y ago>Why did POWER10 become less open, requiring binary blobs? Well the article did actually state it: avoiding Power10's notorious binary firmware requirement for OMI RAM and I/O. It is the requirement for OMI RAM and I/O. Not the CPU itself.
- deleted 3y ago[deleted]
- hamandcheese 3y ago> they made available a platform which for its entire lifespan up until that point, hadn't evolved under the same pressures as the existing x86 CPU market, but instead in an environment in which there was really no natural motive for them to lock things down at the CPU level. What is the natural motivation for x86 manufactures to lock their CPUs down?
- ThinkBeat 3y agoTo send out a "press release" (of sorts) to announce a new series of machines based around a CPU that does not exist a CPU with a tiny niche market a company that is mysteriously unknown a company that has never produced (designed) a CPU before. a company that is dedicated to "stealth" mode a company that does not yet know how much the CPUs will cost. Seems like an extremely risky strategy. How much is it likely to cost to have an advanced CPU manufactured in a tiny quantity? Can a fab just "change cpu type/model" and produce them? (None to low "setup" fee?
- sylware 3y ago... and big endian???
- donatzsky 3y agoAccording to the blog post, it's bi-endian.
- formerly_proven 3y agoYou're probably going to run Linux on these which means you're going to use the ppc64le port.
- deleted 3y ago[deleted]
- speed_spread 3y agoMy guess is that this new CPU is just an IBM-licensed POWER10 that will have the mandatory blob removed or open sourced.
- airtonix 3y ago[dead]
- _a_a_a_ 3y agoA bit of context from the post: "Raptor yesterday officially announced that we're not getting Power10 systems. The idea is we're going to be getting something better: the Solid Silicon S1. It's Power ISA 3.1 and fully compatible, but it's also a fully blob-free OpenPOWER successor to the POWER9, avoiding Power10's notorious binary firmware requirement for OMI RAM and I/O. "
- aorth 3y ago> I'd like to first start out by saying I've been aware of new developments but made certain promises to keep my mouth shut until all the parties were ready to announce. (Phoronix is not so constrained.) I don't understand. Both this and Phoronix's coverage https://www.phoronix.com/news/Raptor-Computing-New-2024 https://www.phoronix.com/news/Raptor-Computing-New-2024 were posted on October 20th. This seems unnecessarily snarky unless there was something more specific. People rag on Phoronix, perhaps sometimes rightly so, but I've seen him wait for media embargos in the past.