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I expect RISC-V chips with a "x86 acceleration" mode will actually be a thing. From either AMD or Intel. And they will succeed.

• musicale 3y ago
  On the ARM side Apple Silicon has an x86 memory ordering mode for Rosetta 2.
  • snvzz 3y ago
    I suppose AMD and Intel would likely implement (or reuse) a full-blown frontend under a processor mode. Likely, limited to usermode.