2 ms·
it's just a bunch of (virtual) CPU state changes, really easy to read if you've ever simulated a CPU before. Take the INY instruction for example. it does: i
by philsnow 15y ago
it's just a bunch of (virtual) CPU state changes, really easy to read if you've ever simulated a CPU before. Take the INY instruction for example. it does: increment Y register, set the Z(ero) flag/bit to whether Y is now equal to zero, set the N(egative) flat/bit to whether Y is now less than zero.
Or BNE (branch not equal): if the last instruction (hopefully a compare) set the Z(ero) flag, jump ahead t instructions. otherwise don't do anything.
Maybe notch has asserted that if he can't fit what an instruction does in ~60 characters, that instruction is doing too much
- hackermom 15y ago"...if the last instruction..." I know this sounds like nitpicking, but that mistake right there has caused many a 6502 emulators to produce erroneous results. The 6502 core's status register is resident and the flags in it are changed only when an op-code directly does so; it never "resets" arbitrarily, so proper conditionals that act on a specific status flag can actually occur far and wide between the op-code that actually affected that one specific flag.
- philsnow 15y agoI don't know if the behavior you describe is commonplace on other cpus, but it seems quite reasonable, if only because it greatly reduces the complexity of the emulator because not every instruction has to touch every status register. What would JMP set the Z(ero) or N(egative) status bits to anyway? I've only briefly glanced through the dcpu-16 spec, but it doesn't seem to explicitly call Z or N by the names I've imputed, I think they're just regular registers that get used for a certain purpose sometimes. "this _sounds_ like nitpicking" when emulating a cpu, there's nothing but nits. pick away :)