3 ms·
Just to check my understanding -- there's a 10x10 mm active interposer here, which has 64 "management-class" (MMU-less, I assume) cores, a crapload of interconn
by addaon 3y ago
Just to check my understanding -- there's a 10x10 mm active interposer here, which has 64 "management-class" (MMU-less, I assume) cores, a crapload of interconnect, and a decent amount of I/O; and this can support up to a 5x5 array of chiplets bonded on top, each of which (of the current three) is either a quad core "application-class" processor (but still in-order), a tiny little FPGA (big question seems to be the width/capability of the DSP blocks), or something AI-ish that doesn't really interest me. Yes?
One question that immediately comes to mind is if there are a few pins on the interposer that are basically pass-through to the 2 x 2 mm chiplet on top, so that a chiplet that provides some level of I/O beyond what the interposer already has can be supported. I assume the UCIe links or something can be used as generic high speed SERDESes for that sort of use case, but more thinking about radar FEs and such.
- adapteva 3y agoIt's a 4x4 array of chiplets, the rest is UCIe/IO logic. the ebricks do have some pass throughs, but real IO capability is done through UCIe based chiplets.
- addaon 3y agoThanks. I'm trying to think of cases where (assuming no use of the AI stuff) this actually ends up cheaper/smaller than just embedding 16x a tile's compute cores (or a smaller number of much higher performance cores) and 16x a tile's FPGA fabric... with such a small number of options and small number of tiles, I'd suspect (but could easily be wrong) that the area overhead for bonding is on the same order of magnitude as the actual logic here. And while having a large number of fast cores scattered through FPGA fabric would be /relatively/ novel, it seems like it would support the type of flexible configurability that's needed here. I could imagine that this grows in power with a growing ecosystem of tiles, but I'm stretching my mind here for tiles that actually need to be ASICs instead of just implemented in fabric.
- adapteva 3y agoYeah, I have been struggling with these questions for 25 years and I am not alone.:-) You can always spend $100M and build exactly what you need (eg. 16 RISC-V processors with custom vector extensions and a selection of I/), HBM3, serdes, ...). If you are lucky your with your application fit (cost, power, performance) you could possibly buy a Snapdragon, Xavier, Versal, Agilex. The problem we are addressing is the gap, where you don't have $100M in your pocket and you are constrained by physics (size, weight power) or cost.
- namibj 3y agoIn similar manner: "what about silicon photonics?" IIUC fiber transceivers have become better than baseband copper differential pair transceivers for same-rack cluster interconnects. And the main issue with them is packaging difficulty/needing to have a cheap link to the switching fabric data plane, if these benefits are to remain strong after accounting for the overhead that result from not being able to integrate the PHY on the same die as the fabric data plane. Both efficiency and cost.
- adapteva 3y agoYes, you are right that pseudo-integrated silicon-photonics is really exciting! The Ayar Labs + Intel FPGA chiplet combo based on AIB is a great example. Packaging is one of the really big challenges, DARPA invested ~$100M to solve this problem with the PIPES program.