3 ms·
This comes up all the time in the context of DRAM routing. See e.g. the first image at https://resources.altium.com/p/pcb-routing-guidelines-ddr4-memory-devices
by addaon 3y ago
This comes up all the time in the context of DRAM routing. See e.g. the first image at https://resources.altium.com/p/pcb-routing-guidelines-ddr4-memory-devices https://resources.altium.com/p/pcb-routing-guidelines-ddr4-m....
- mensetmanusman 3y agoOkay in this case impedance matching is more important than the time delay. Thanks for the link :)