4 ms·

>for example the interrupt controller in a modern ARM SoC is more complex than a RISC-V core. RISC-V has the AIA[0], a pretty good interrupt controller. It is

by snvzz 3y ago

>for example the interrupt controller in a modern ARM SoC is more complex than a RISC-V core. RISC-V has the AIA[0], a pretty good interrupt controller. It is a requirement in the platform spec. https://github.com/riscv/riscv-aia https://github.com/riscv/riscv-aia