> Was this mentioned anywhere or just a guess? Yeah, they're burying it a bit, but it's on their third slide. > RV64G + 32-bit instructions for code size is b

> Was this mentioned anywhere or just a guess? Yeah, they're burying it a bit, but it's on their third slide. > RV64G + 32-bit instructions for code size is best in class > • More ld/st addressing modes > • Ld/st pair > • Conditional immediate branches > • Move pair Those are all custom extensions to Qualcomm's design, and suspiciously all how AArch64 gets passable code density. > This is interesting, and if true I would just add that they would likely sell both cores – one RISC-V and one ARM – at least in the short term. Proof is that they have already taped out and anounced thier NUVIA based Snapdragon X desktop/laptop SoC. Them announcing that is what made ARM sue them. That core as an AArch64 design is going to be stuck in the courts for longer than it'll be relevant. This work by Qualcomm seems to be a combo of trying to get anything out of the NUVIA acquisition, and maybe having a stick when negotiating a settlement with ARM ("we'll make your existential threat more real").