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I disagree with the author's point that CPU instruction sets should expose more of the CPU's implementation. This has been tried in the past and failed to work
by ndiddy 3y ago
I disagree with the author's point that CPU instruction sets should expose more of the CPU's implementation. This has been tried in the past and failed to work long-term. One example of this is branch delay slots from some RISC processors (such as MIPS and SuperH) designed in the late 80s and early 90s. For those unfamiliar with the concept, it basically means that the instruction after a branch instruction will get run regardless of if the branch was taken or not. This was a short-term benefit, as it meant the job of avoiding pipeline stalls after a branch was left to the programmer, so the processor could be simpler and cheaper than designs without them. However, as time went on, the processor designs evolved with more complex pipelines, so the single instruction wasn't enough to cover the branch delay. Instead, it became a legacy issue that future processors had to deal with for compatibility reasons and made their branch prediction and pipeline logic more complex.
- danielmarkbruce 3y agoI don't think he's saying "expose random implementation details". Exposing the wrong details would obviously be bad. He's just saying c's model has significant shortcomings in the world of modern CPUs.
- rewmie 3y ago> he's saying c's model just doesn't work well anymore. The author argues that C's model does not fit the model he defined himself and claims to be the same model used by everyone. After going through the article, I'm left with the impression that the author's thesis is flawed and relies on a series of strawmen arguments. Among the strawmen we find: * arguing that speculative execution "were added to let C programmers continue to believe they were programming in a low-level language". * claiming that "modern processors are trying to emulate "the same abstract machine as a PDP-11" * "Creating a new thread is a library operation known to be expensive, so processors wishing to keep their execution units busy running C code rely on ILP (instruction-level parallelism)." * etc etc etc. I don't think this opinion piece is grounded on reality, let alone is an objective take.
- danielmarkbruce 3y agoHe doesn't define a model. He just discusses the gap between c's model and a few details of a modern CPU and talks about a few other models. In your opinion, why was speculative execution added? It doesn't seem off base to suggest it was to enable programmers to continue writing single threaded applications while increasing execution speed. In your opinion, what is wrong with the statement that modern processors are trying to emulate an abstract machine like PDP-11? To me it seems largely right.
- dataflow 3y ago> One example of this is branch delay slots That's the only example I'm aware of. Are there others? (I'm sure you could do it poorly if you wanted to, but how much history is there to extrapolate from?)
- JonChesterfield 3y agoI'm unimpressed that x64 assumes function calls write the return address to stack memory instead of passing it in a register. It means you have to use the stack memory in order to benefit from the call/ret prediction hardware, even in functions which don't otherwise need to allocate any stack memory. In general leaking microarch weirdness matters less if you don't have backwards compatibility.
- fanf2 3y agoVector instruction sets expose too much about the size of the CPU. They have got bigger over the years, 128 - 256 - 512 bits, 8 - 16 - 32 registers, and now Intel is struggling to fit them comfortably into their small efficiency cores and retain binary compatibility with their big performance cores.
- frankreyes 3y agoWasn't this also similar for itanium? Where the branch burden would be on the compiler?
- bayindirh 3y agoCounterpoint: Allowing explicit control over prefetching or providing an additional "engine" which brings in data to caches in a pattern you like is esp. beneficial in real-time and latency sensitive applications. I have listened a talk where developers used such subsystem in the given processor. If unused, they would spend 95% of their time window just to copy the data, however by requesting the data ahead of time via that engine, they only used 10% of their time window to get the data, and accomplished what they wanted in ~50% of the time window they have, leaving tons of time for further features and improvements. If x86 had a such feature, I'd use that in my Ph.D. to request the matrix data I'm accessing ahead of time, because the pattern I use is not linear but well defined. Now, if I want to accelerate that code further, I need to reorder my matrices to make the prefetcher happy, and refactor the whole codebase from top to bottom.
- theamk 3y agogeneric x86 does not, but SSE extension (present on all modern CPUs) does have it! and you naturally can use C to call it via intrinsics, because C is low level after all... https://stackoverflow.com/questions/48994494/how-to-properly-use-prefetch-instructions https://stackoverflow.com/questions/48994494/how-to-properly...
- JonChesterfield 3y agoYou may like the x86 instruction called 'prefetch'.
- monocasa 3y agoPREFETCHh: Prefetch Data Into Caches https://c9x.me/x86/html/file_module_x86_id_252.html https://c9x.me/x86/html/file_module_x86_id_252.html