> This also makes them exceptionally power-efficient ... > Single-cycle instruction execution For what it's worth, single cycle execution is really a detrimen

> This also makes them exceptionally power-efficient ... > Single-cycle instruction execution For what it's worth, single cycle execution is really a detriment to power efficiency. There is an optimal logic level per pipeline stage for CMOS processes which will minimize power (and it's usually quite small!). Extremely deep pipelining lets you hit a higher Fmax, but if you don't crank up the frequency you will often save quite a bit of power.