One of the assertions of RISC is that microcode is a performance penalty, to be avoided. And many have. "To provide this rich set of instructions, CPUs used m

One of the assertions of RISC is that microcode is a performance penalty, to be avoided. And many have. "To provide this rich set of instructions, CPUs used microcode to decode the user-visible instruction into a series of internal operations. This microcode represented perhaps 1⁄4 to 1⁄3 of the transistors of the overall design. If... the majority of these opcodes would never be used in practice, then this significant resource was being wasted." https://en.m.wikipedia.org/wiki/Berkeley_RISC https://en.m.wikipedia.org/wiki/Berkeley_RISC