> This would be fixed if C insns "always came in pairs" (at the expense of some extra C.NOP's) but they don't. The ISA manual hints at this: with regular inst

> This would be fixed if C insns "always came in pairs" (at the expense of some extra C.NOP's) but they don't. The ISA manual hints at this: with regular instructions allowed to be 16b aligned, regular & C instructions can be mixed freely. This also helps improve the code density. Requiring C instructions to come in pairs, reduces that advantage. So it's a kind of all-or-nothing affair. Probably RISC-V designers ran a bunch of code simulations, and concluded that "mix regular & C instructions freely" weighed heavier than "simplify RISC-V cpu designs that support C subset". Note that cpu design effort is a 1-time cost (when designing new cpu). Whereas adding spurious NOPs would be a recurring cost for all software using the C subset.