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Speculating a bit here: Perhaps one could even create a JIT that generates different code for Intel P-cores and E-cores in the same process. However, that would
by unnah 3y ago
Speculating a bit here: Perhaps one could even create a JIT that generates different code for Intel P-cores and E-cores in the same process. However, that would be very challenging to get working if the OS can switch the process from one core to another at any time.
The runtime would basically have to detect which AVX-512 instruction has failed at any point in the compiled code, map the processor state to AVX-2 registers and jump to an equivalent AVX2 code path. It would probably be easier to build the implementation on software transactions that can be restarted at coarse granularity, i.e. something like STM.
- pjmlp 3y agoHow do you imagine Android works across high and lower power ARM cores? However ART is also a great piece of engineering at JVM and CLR level, even though Dalvik was quite lame, even when compared against Nokia and Sony-Ericson J2ME implementations. ART is another level. Nowadays you have an handwritten Assembly interpreter for faster startup, a JIT compiler, that also gathers PGO data, and an AOT compiler that picks up that data when the device is idle taking all the required optimizations. To take this even furter, those PGO files are uploaded into the Play Store, and shared across compatible devices when applications are downloaded, not only allows jumping straight into JIT with PGO data, all devices collaborate gathering PGO data that covers all common use cases across the application audience. And yes this also takes into account the ARM architectures. On the JVM side, IBM and Azul have similar offerings with cloud based JITs for their implementations.
- unnah 3y agoI thought ARM big.little implementations supported the exact same instruction set on both big and little cores. Don't they?
- pjmlp 3y agoNo, they are different ARM ISAs. https://www.arm.com/technologies/big-little https://www.arm.com/technologies/big-little
- RaisingSpear 3y agobig.LITTLE allows a hybrid microarchitecture, but all cores must support the same instruction set architecture. Even SVE must use the same vector width across all cores, which makes it unlikely that >128b SIMD will ever show up on consumer cores in the near future: https://gist.github.com/zingaburga/805669eb891c820bd220418ee3f0d6bd#sve2---scaling-from-128-bit-to-128-bit https://gist.github.com/zingaburga/805669eb891c820bd220418ee...
- pjmlp 3y agoNo they don't, picking the first example "Armv9.2 - DynamIQ big.LITTLE - DynamIQ Shared Units-120" https://developer.arm.com/documentation/102484/0001/The-Cortex-X4--core/Supported-standards-and-specifications?lang=en https://developer.arm.com/documentation/102484/0001/The-Cort... https://developer.arm.com/Processors/Cortex-A720 https://developer.arm.com/Processors/Cortex-A720 https://developer.arm.com/Processors/Cortex-A520 https://developer.arm.com/Processors/Cortex-A520 You will notice that for e.g. Asymmetric MTE isn't supported across all of them, and the differences in microarchitecture are enough to have impact in the kind of instructions being used.
- RaisingSpear 3y agoYour first link comes up as blank for me (documentation-service.arm.com returns 404 for me). But it's worth pointing out that X4, A720 and A520 support asymmetric MTE [1] - just the A720 page you linked to fails to mention it. [1] https://www.arm.com/blogs/blueprint/memory-safety-arm-memory-tagging-extension#h-what-is-arm-s-latest-mte-development https://www.arm.com/blogs/blueprint/memory-safety-arm-memory...
- Symmetry 3y agoI'm not sure the parenthetical "including Asymmetric MTE" in one doesn't mean it isn't present in the other, especially since the lists are otherwise in different orders and just generally seem to be written by different persons.
- tveita 3y ago