Furthermore, IMO calling an ISA only one of 'vector' or 'SIMD' based on whether it has VL doesn't make sense - semantically, VL is a subset of masking (if you w

Furthermore, IMO calling an ISA only one of 'vector' or 'SIMD' based on whether it has VL doesn't make sense - semantically, VL is a subset of masking (if you want VL & a mask, just and them), whether hardware will short-circuit on it entirely depends on the hardware, and could be done on both. All RVV hardware that I know of takes the same amount of time for VL=1 and VL=max. (and defining vector vs SIMD by existence of non-fixed register width excludes Cray-1, which you do not want to do)