3 ms·

This is at least somewhat wrong at best - SVE2 doesn't have a dynamic vector length like RVV (only non-fixed hardware register width, and masking), and Cray-1,

by dzaima 3y ago

This is at least somewhat wrong at best - SVE2 doesn't have a dynamic vector length like RVV (only non-fixed hardware register width, and masking), and Cray-1, said to be the first vector processor, has a fixed hardware register size (64 elements, each 64 bits). So either SVE2 isn't vector due to lack of VL, or AVX-512/AVX10 is vector if VL isn't necessary (the only difference between AVX and SVE2 being the scalable registers, which Cray-1 doesn't have).

dzaima 3y ago
Furthermore, IMO calling an ISA only one of 'vector' or 'SIMD' based on whether it has VL doesn't make sense - semantically, VL is a subset of masking (if you want VL & a mask, just and them), whether hardware will short-circuit on it entirely depends on the hardware, and could be done on both. All RVV hardware that I know of takes the same amount of time for VL=1 and VL=max. (and defining vector vs SIMD by existence of non-fixed register width excludes Cray-1, which you do not want to do)
RaisingSpear 3y ago
> SVE2 doesn't have a dynamic vector length like RVV SVE and RVV are no different in that regard. Note that RVV's VL doesn't alter the vector length - it's just an alternative way of masking (which can easily be implemented in SVE).
- dzaima 3y ago
  Yes, I agree that VL isn't meaningfully distinct from masking as I noted in a sibling reply; regardless, some definitions of SIMD vs vector rely on it, e.g. wikipedia: https://en.wikipedia.org/wiki/Vector_processor#Comparison_with_modern_architectures https://en.wikipedia.org/wiki/Vector_processor#Comparison_wi...
  - RaisingSpear 3y ago
    This doesn't sound quite right - RVV has 100% fixed length vectors that can't vary in length. If setting VL is enough to qualify (which seems to be such a minor differentiating factor), then I'd argue that SVE also qualifies since you can use WHILELT to do exactly the same thing as setting VL. SVE2.1 basically makes the whole thing identical, with its support for predicate-as-counter.
    - dzaima 3y ago
      Again, I pretty much agree. WHILELT makes RVV-equivalent things trivial, but it's just a data→data instruction that could be done in AVX-512 too, as it's just a scalar (1<<n)-1, so the SVE2 & AVX separation in snvzz's original message is still unexplained. (assuming they don't mean to exclude Cray-1; unless they did mean SVE2.1? or maybe actually AVX (AVX1) and not AVX-512/AVX10? though even there you can still mask things to some limited extent) SVE2.1 predicate-as-counter seems interesting, but I can't find any overview of it (only specific instructions/intrinsics), would you happen to know of any?
      - RaisingSpear 3y ago
        > would you happen to know of any? I doubt I know any more than you. ARM's info on the matter is a little scarce, and I struggle to understand their documentation at times.

by dzaima 3y ago

dzaima 3y ago

Furthermore, IMO calling an ISA only one of 'vector' or 'SIMD' based on whether it has VL doesn't make sense - semantically, VL is a subset of masking (if you want VL & a mask, just and them), whether hardware will short-circuit on it entirely depends on the hardware, and could be done on both. All RVV hardware that I know of takes the same amount of time for VL=1 and VL=max. (and defining vector vs SIMD by existence of non-fixed register width excludes Cray-1, which you do not want to do)

RaisingSpear 3y ago

> SVE2 doesn't have a dynamic vector length like RVV SVE and RVV are no different in that regard. Note that RVV's VL doesn't alter the vector length - it's just an alternative way of masking (which can easily be implemented in SVE).

dzaima 3y ago
Yes, I agree that VL isn't meaningfully distinct from masking as I noted in a sibling reply; regardless, some definitions of SIMD vs vector rely on it, e.g. wikipedia: https://en.wikipedia.org/wiki/Vector_processor#Comparison_with_modern_architectures https://en.wikipedia.org/wiki/Vector_processor#Comparison_wi...
- RaisingSpear 3y ago
  This doesn't sound quite right - RVV has 100% fixed length vectors that can't vary in length. If setting VL is enough to qualify (which seems to be such a minor differentiating factor), then I'd argue that SVE also qualifies since you can use WHILELT to do exactly the same thing as setting VL. SVE2.1 basically makes the whole thing identical, with its support for predicate-as-counter.
  - dzaima 3y ago
    Again, I pretty much agree. WHILELT makes RVV-equivalent things trivial, but it's just a data→data instruction that could be done in AVX-512 too, as it's just a scalar (1<<n)-1, so the SVE2 & AVX separation in snvzz's original message is still unexplained. (assuming they don't mean to exclude Cray-1; unless they did mean SVE2.1? or maybe actually AVX (AVX1) and not AVX-512/AVX10? though even there you can still mask things to some limited extent) SVE2.1 predicate-as-counter seems interesting, but I can't find any overview of it (only specific instructions/intrinsics), would you happen to know of any?
    - RaisingSpear 3y ago
      > would you happen to know of any? I doubt I know any more than you. ARM's info on the matter is a little scarce, and I struggle to understand their documentation at times.