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100%. RISC-V at least requires a macro assembler of some kind to be more pleasant. That's not to say RISC-V isn't a good ISA. The whole point of RISC is to be
by cmrdporcupine 3y ago
100%. RISC-V at least requires a macro assembler of some kind to be more pleasant.
That's not to say RISC-V isn't a good ISA. The whole point of RISC is to be a good target for compilation, not humans.
- sylware 3y agoI severely disagree, I think that a "good enough" and "free" and world-wide ISA standard is meant for assembly programming. I meant a lot more, like all system components and very high level language interpreters (javascript/lua/python/insert_your_high_level_language_here). I did not mean zero preprocessor, I meant a conservative/frugal usage a simple pre-processor to avoid to spawn another insanely complex SDK dependency of the code which will be a pain to create a real life alternative. Basically, RISC-V is meant for multi-instructions per line assemblers (semi-colon...).
- snvzz 3y agoThere's no real reason to code in machine code, or to give up the convenience of a macro assembler and use a micro assembler. But you can do both with RISC-V, there's nothing to stop you.
- cmrdporcupine 3y agoAbsolutely, and I've done it. But as far as various assemblers go, RISC-V is one of the least ergonomic. It's consistent, certainly. But tedious.
- snvzz 3y agoI have done it, too. RISC-V Feels like MIPS, except better. m68k used to be my favorite, until RISC-V happened.
- pjmlp 3y agoTraditional with the MIPS CPU linage, as many instructions common in other ISAs, only exist as macros.