Now that op fusion has been implemented for this idiom, the cost of a new instruction does not seem worth the benefit. The benefit would be only a tiny improve

Now that op fusion has been implemented for this idiom, the cost of a new instruction does not seem worth the benefit. The benefit would be only a tiny improvement in code size, and that's restricted to when the compiler can be absolutely certain that the target CPU is going to be modern enough to support it. So, in practice, for many, many years, this benefit would be almost never reaped. This is not a new topic in the design of ISAs and their implementations in silicon. Idiom recognition and optimization has long existed in x86, ARM, and I'm sure other old ISA implementations. RISC-V can avoid it by adding dedicated instructions because it's just getting started (relatively speaking), but even so, I'm sure there will be opportunities for idiom recognition and optimization that RISC-V implementers will take.