If you're interested in low-power embedded, the WCH chip there has two powersaving modes; at 3.3V (it is 5V tolerant). At the lowest-power mode, the whole SoC c

If you're interested in low-power embedded, the WCH chip there has two powersaving modes; at 3.3V (it is 5V tolerant). At the lowest-power mode, the whole SoC consumes 9uA, and has a wakeup time of 200us. I wonder how much extra oomph the chip would get if there was a lower-speed power-saving mode – although I am ignorant about whether this would be compatible with SRAM.