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Can I ask why more manufacturers don't implement apple's strategy with soc with ram and all and offer option to add additional classic ram as a slower cache buf

Can I ask why more manufacturers don't implement apple's strategy with soc with ram and all and offer option to add additional classic ram as a slower cache buffer between soc&ssd? This should both solve the lack of upgradability and unlock more performance per watt?

segfaultex 3y ago
Money. Sounds reductive, but I think oems don’t see much demand for an architecture that implements both. So they’ll go with one or the other.
zamadatix 3y ago
Intel did this is the Sapphire Rapids xeons via 64 GB HBM built in and DDR 5 slots. L4 cache is also not unheard of, having been tried a few times for well of a decade. The downsides are cost/complexity for relatively little gain.
rajnathani 3y ago
Your comment is ambiguous, but if you’re implying that Apple does this then it’s incorrect. They just have “unified memory” (i.e. the high bandwidth SoC substrate memory).
- Moldoteck 3y ago
  Yes, and I'm asking why not allow to add extra ram through slots as a slower cache between unified mem and ssd? And why other manufacturers are not doing this to achieve apple lvl of performanca and also allowing upgradability
  - rajnathani 3y ago
    One of the neighboring comments citing Intel’s HBM memory I guess does the 2-layer memory thing. The reason we probably don’t see these dual-level memory solutions is that the fast-access part of the memory of HBM is really expensive to implement on the same substrate as the SoC. For example, part of the reason why top-end GPUs are expensive (besides “pricing power in the age of AI”) is that they all have HBM memory. DDR based memories are super-cheap in comparison to implement in hardware. Also another aspect is that the SoC needs to support HBM memory, most chips of yesteryears simply have DDR<n> support only.
  - cma 3y ago
    I thought slots don't really slow things down much and aren't the primary source of latency, isn't it more about cost and power? Adding slots back in would remove the cost and power advantages wouldn't they? And now using more SRAM to track occupancy of an extra layer of cache, or if not SRAM for that something adding more latency.

segfaultex 3y ago

Money. Sounds reductive, but I think oems don’t see much demand for an architecture that implements both. So they’ll go with one or the other.

zamadatix 3y ago

Intel did this is the Sapphire Rapids xeons via 64 GB HBM built in and DDR 5 slots. L4 cache is also not unheard of, having been tried a few times for well of a decade. The downsides are cost/complexity for relatively little gain.

rajnathani 3y ago

Your comment is ambiguous, but if you’re implying that Apple does this then it’s incorrect. They just have “unified memory” (i.e. the high bandwidth SoC substrate memory).

Moldoteck 3y ago
Yes, and I'm asking why not allow to add extra ram through slots as a slower cache between unified mem and ssd? And why other manufacturers are not doing this to achieve apple lvl of performanca and also allowing upgradability
- rajnathani 3y ago
  One of the neighboring comments citing Intel’s HBM memory I guess does the 2-layer memory thing. The reason we probably don’t see these dual-level memory solutions is that the fast-access part of the memory of HBM is really expensive to implement on the same substrate as the SoC. For example, part of the reason why top-end GPUs are expensive (besides “pricing power in the age of AI”) is that they all have HBM memory. DDR based memories are super-cheap in comparison to implement in hardware. Also another aspect is that the SoC needs to support HBM memory, most chips of yesteryears simply have DDR<n> support only.
- cma 3y ago
  I thought slots don't really slow things down much and aren't the primary source of latency, isn't it more about cost and power? Adding slots back in would remove the cost and power advantages wouldn't they? And now using more SRAM to track occupancy of an extra layer of cache, or if not SRAM for that something adding more latency.