4 ms·

> On an FPGA, additional logic does not slow down the other logic. It absolutely does. As the amount of logic in a design increases, it becomes increasingly di

> On an FPGA, additional logic does not slow down the other logic. It absolutely does. As the amount of logic in a design increases, it becomes increasingly difficult (and, eventually, impossible) for a place-and-route algorithm to generate a layout which meets timing constraints.

nisegami 3y ago
Maybe my understanding of FPGAs is wrong, but isn't that an issue at design-time and not an issue at run-time?
- lstodd 3y ago
  Well if you declare that anything your router can't place can not exist then yes. But in reality - no. There's a reason why people didn't already drop everything in favor of FPGAs and it's because they don't scale (and also are horrible at thermals).
  - a96 3y ago
    Also, cost. And tools.
LoganDark 3y ago
Oops. I was thinking of specifically the case where each "container" was already confined to its own space on the chip, so placing/routing would happen individually. But in the general case it does make sense that more logic in the middle of some code will affect everything that has to be placed around it.