Aside from what others have said about greater bit width only being useful for large fetches, there's also circuitry necessary to allow more parallel fetches fr

Aside from what others have said about greater bit width only being useful for large fetches, there's also circuitry necessary to allow more parallel fetches from the L1 to other parts of the memory subsystem (for Intel, these are called line fill buffer) and they're the real limiting factor for single threaded memory bandwidth (at least on that platform). For whole chip bandwidth this isn't as much of an issue, but the things others have said are true there still.