Excellent, they kept the SMI bus, which I was afraid would disappear when they started to make their own silicon. If you have an FPGA, it’s trivial to implemen

Excellent, they kept the SMI bus, which I was afraid would disappear when they started to make their own silicon. If you have an FPGA, it’s trivial to implement a fast, high-bandwidth, low-latency, pi-as-master, bidirectional bus with (supported, even) DMA into user-space over SMI (secondary memory interface). You will lose basically all your GPIO if you go with the normal 16-bit interface, but hey, you have an FPGA…