4 ms·
RP1: The silicon controlling Raspberry Pi 5 I/O
- spacedcowboy 3y agoExcellent, they kept the SMI bus, which I was afraid would disappear when they started to make their own silicon. If you have an FPGA, it’s trivial to implement a fast, high-bandwidth, low-latency, pi-as-master, bidirectional bus with (supported, even) DMA into user-space over SMI (secondary memory interface). You will lose basically all your GPIO if you go with the normal 16-bit interface, but hey, you have an FPGA…
- jeroen79 3y agoWhy do they suddenly need an extra chip for this?, is the BCM2712 stagnating on features?
- justin66 3y agoNothing sudden about it. They were working on it since 2015 [0]. As for the rest, for starters, watch their recent videos? [0] https://www.raspberrypi.com/news/rp1-the-silicon-controlling-raspberry-pi-5-i-o-designed-here-at-raspberry-pi/ https://www.raspberrypi.com/news/rp1-the-silicon-controlling...