4 ms·
My understanding is that the hardware turned out to use way more power than expected. The whole premise of the design was that the extra registers between logi
by bcrl 3y ago
My understanding is that the hardware turned out to use way more power than expected. The whole premise of the design was that the extra registers between logic stages were "free". In the real world, pipelining has a significant power cost.
- FullyFunctional 3y agoAre you talking about Achronix? Because they certainly did tell me that power was the reason they bailed on their original approach. Space-Time ran hot, but I don’t see why they would be using more flip-flops than with a conventional FPGA. Also my sources were pretty clear on the cause of their failure.