3 ms·

If they've done that, I think the concept of "turning off" a device goes away. You just unplug it, and the energy needed to dump the stuff in the pipeline to me

If they've done that, I think the concept of "turning off" a device goes away. You just unplug it, and the energy needed to dump the stuff in the pipeline to memory can be stored in a capacitor. The OS can just always be loaded and ready to go; when power is restored it checks to see if the hardware has changed and just loads up the 64 MB of CPU cache. It could take just a few milliseconds. It takes on the order of a millisecond to charge the capacitors in a desktop PSU. "Restarting" becomes basically the same thing as reloading, and takes >100s of times longer than actually restarting the device. That's crazy to consider. If boot time is 0, stuff will just unplug itself after its been idle for a few seconds. I'd expect the hardware in phones/laptops to become more distributed, with basic vital functions handled by a separate processor. Probably the screen gets taken over by a very simple processor that can only display the time, battery %, cell info (or the current screen buffer, for a laptop) and user input causes the main cpu to wake up in between frames.

benj111 3y ago
Why do you even need a cpu cache? 1ns write operations suggest fast read too.
- vlovich123 3y ago
  You’d probably still need an L1 cache. L2 and L3 might be superfluous or you could have massive L2/L3 caches made with this rather than traditional SRAM that sit internally within the CPU to avoid the memory bus. Contention for the memory bus could also be a reason to still have SRAM caches that are slower than main memory. Shifts like this are so impactful it’s hard to predict exactly what good designs will look like until we’ve had 5-10 years hands on for the industry to shake out how the Hw topology will looks like (maybe more since HW dev cycles prevent fast iteration and testing of ideas)
- hwillis 3y ago
  Should be stressed that speed is entirely theoretical: https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103 https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101... > In all of the above tests, the program and erase states were set using between 1 and 10 ms voltage pulses, two times longer than the switching times used in our recent report of ULTRARAM on GaAs substrates.[15] In both cases, the devices operate at a remarkably high speed for their large (20 μm) feature size. Assuming ideal capacitive scaling[33] down to state-of-the-art feature sizes, the switching performance would be faster than DRAM, although testing on smaller feature size devices is required to confirm this. > Why do you even need a cpu cache? Cell read time is entirely different from latency and throughput. This stuff still reads in rows like RAM and can't just be accessed freely like registers.
- Tuna-Fish 3y ago
  No matter how fast the device itself is, addressing into a large pool will always be slower than a smaller pool. Both because of increased travel distance, and because every time you double the size of the pool, you add one additional mux on the path between the request and the memory. This is why CPUs have multi-level caches, even though the transistors in L1 cache and L2 cache are typically the same -- the difference in access latency is not because L2 is made of slower memory, but because L1 is a very small pool very close to the CPU with the load/store units built into it, and L2 is a bit further away. However, if main memory latency is suddenly a lot lower, it might change what is the most efficient cache level layout. The currently ubiquitous large L3 cache might go away. That would of course require very high bandwidth to the memory chips, because L3 does bandwidth amplification too.
sowbug 3y ago
Will "have you tried unplugging it?" still be the ultimate tech-support solution if persistent RAM becomes commonplace?
stcredzero 3y ago
If they've done that, I think the concept of "turning off" a device goes away. ...The OS can just always be loaded and ready to go; when power is restored it checks to see if the hardware has changed and just loads up the 64 MB of CPU cache. The idea, called “Orthogonal Persistence” way back when, has been around quite awhile. Here’s my (probably spotty) idea of the history: Researchers wanted instant-on for their early visions of tablets. To make sure security and networking would still work properly, there was an idea to use Capabilities (which were around since the 1960’s) to support this and solve the chicken and egg problems that were thought to arise. Capabilities later became widely adopted just for better security, but Orthogonal Persistence never took off, because never rebooting would have required much higher levels of reliability, which would have been expensive to achieve. So today’s devices still reboot, but also have a fast "wake from sleep." So I’m not sure if we will ever have true “Orthogonal Persistence.” We might have much slicker “wake from sleep” instead. I'd expect the hardware in phones/laptops to become more distributed, with basic vital functions handled by a separate processor. This is already the case!
Weryj 3y ago
We thought that with Optane, I'm sad to see that discontinued because it was a much better target for swap files or databases.

benj111 3y ago

Why do you even need a cpu cache? 1ns write operations suggest fast read too.

vlovich123 3y ago
You’d probably still need an L1 cache. L2 and L3 might be superfluous or you could have massive L2/L3 caches made with this rather than traditional SRAM that sit internally within the CPU to avoid the memory bus. Contention for the memory bus could also be a reason to still have SRAM caches that are slower than main memory. Shifts like this are so impactful it’s hard to predict exactly what good designs will look like until we’ve had 5-10 years hands on for the industry to shake out how the Hw topology will looks like (maybe more since HW dev cycles prevent fast iteration and testing of ideas)
hwillis 3y ago
Should be stressed that speed is entirely theoretical: https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103 https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101... > In all of the above tests, the program and erase states were set using between 1 and 10 ms voltage pulses, two times longer than the switching times used in our recent report of ULTRARAM on GaAs substrates.[15] In both cases, the devices operate at a remarkably high speed for their large (20 μm) feature size. Assuming ideal capacitive scaling[33] down to state-of-the-art feature sizes, the switching performance would be faster than DRAM, although testing on smaller feature size devices is required to confirm this. > Why do you even need a cpu cache? Cell read time is entirely different from latency and throughput. This stuff still reads in rows like RAM and can't just be accessed freely like registers.
Tuna-Fish 3y ago
No matter how fast the device itself is, addressing into a large pool will always be slower than a smaller pool. Both because of increased travel distance, and because every time you double the size of the pool, you add one additional mux on the path between the request and the memory. This is why CPUs have multi-level caches, even though the transistors in L1 cache and L2 cache are typically the same -- the difference in access latency is not because L2 is made of slower memory, but because L1 is a very small pool very close to the CPU with the load/store units built into it, and L2 is a bit further away. However, if main memory latency is suddenly a lot lower, it might change what is the most efficient cache level layout. The currently ubiquitous large L3 cache might go away. That would of course require very high bandwidth to the memory chips, because L3 does bandwidth amplification too.

sowbug 3y ago

Will "have you tried unplugging it?" still be the ultimate tech-support solution if persistent RAM becomes commonplace?

stcredzero 3y ago

If they've done that, I think the concept of "turning off" a device goes away. ...The OS can just always be loaded and ready to go; when power is restored it checks to see if the hardware has changed and just loads up the 64 MB of CPU cache. The idea, called “Orthogonal Persistence” way back when, has been around quite awhile. Here’s my (probably spotty) idea of the history: Researchers wanted instant-on for their early visions of tablets. To make sure security and networking would still work properly, there was an idea to use Capabilities (which were around since the 1960’s) to support this and solve the chicken and egg problems that were thought to arise. Capabilities later became widely adopted just for better security, but Orthogonal Persistence never took off, because never rebooting would have required much higher levels of reliability, which would have been expensive to achieve. So today’s devices still reboot, but also have a fast "wake from sleep." So I’m not sure if we will ever have true “Orthogonal Persistence.” We might have much slicker “wake from sleep” instead. I'd expect the hardware in phones/laptops to become more distributed, with basic vital functions handled by a separate processor. This is already the case!

Weryj 3y ago

We thought that with Optane, I'm sad to see that discontinued because it was a much better target for swap files or databases.