3 ms·
1/100 power, 1/10 latency... in a through-hole chip carrier?? How do they get enough of it close enough to the CPU at those low powers and latencies, at DRAM cl
by tuatoru 3y ago
1/100 power, 1/10 latency... in a through-hole chip carrier?? How do they get enough of it close enough to the CPU at those low powers and latencies, at DRAM clocks? Electricity travels 10cm in a tenth of a nanosecond, best case. And it uses quantum...
I'll leave it to the experts.
- duskwuff 3y ago> 1/100 power, 1/10 latency... in a through-hole chip carrier?? That's a common package for testing ICs -- notice the array of dies inside and the haphazardly placed bonding wires. It isn't the final form factor.
- alias_neo 3y agoMy understanding, from reading it, is that the through-hole carrier is for demos. I doubt they've actually demonstrated the speed/power claims practically; that's what the new test kit, and potential fab partnerships are for.
- Tuna-Fish 3y agoThey are talking about the speed of the new type of memory cell, not of the physical implementation they have it in. If this actually pans out, it will be worthwhile to stack a lot of it on the same package as the CPU. The reason memory is so far in current systems is mainly that having it closer wouldn't actually meaningfully help, because almost all the latency is reading data from the DRAM array anyway. If they suddenly get an economical new memory type that has an access latency of tenth of what DRAM does, they are going to figure out how to get it close enough that the signal travel will not be a meaningful part of the total latency.
- tuatoru 3y agoThank you for the explanation! TIL.