4 ms·

Article claims a tenth the latency of dram at 100x lower power, but also says they're trying to fabricate at 20nm. Oh, and also persistent. If they've done tha

Article claims a tenth the latency of dram at 100x lower power, but also says they're trying to fabricate at 20nm. Oh, and also persistent. If they've done that, awesome. Make it, show that it works, licence how to make the thing to semiconductor companies and retire wealthy. Or maybe the university owns the IP.

tuatoru 3y ago
1/100 power, 1/10 latency... in a through-hole chip carrier?? How do they get enough of it close enough to the CPU at those low powers and latencies, at DRAM clocks? Electricity travels 10cm in a tenth of a nanosecond, best case. And it uses quantum... I'll leave it to the experts.
- duskwuff 3y ago
  > 1/100 power, 1/10 latency... in a through-hole chip carrier?? That's a common package for testing ICs -- notice the array of dies inside and the haphazardly placed bonding wires. It isn't the final form factor.
- alias_neo 3y ago
  My understanding, from reading it, is that the through-hole carrier is for demos. I doubt they've actually demonstrated the speed/power claims practically; that's what the new test kit, and potential fab partnerships are for.
- Tuna-Fish 3y ago
  They are talking about the speed of the new type of memory cell, not of the physical implementation they have it in. If this actually pans out, it will be worthwhile to stack a lot of it on the same package as the CPU. The reason memory is so far in current systems is mainly that having it closer wouldn't actually meaningfully help, because almost all the latency is reading data from the DRAM array anyway. If they suddenly get an economical new memory type that has an access latency of tenth of what DRAM does, they are going to figure out how to get it close enough that the signal travel will not be a meaningful part of the total latency.
  - tuatoru 3y ago
    Thank you for the explanation! TIL.
hwillis 3y ago
If they've done that, I think the concept of "turning off" a device goes away. You just unplug it, and the energy needed to dump the stuff in the pipeline to memory can be stored in a capacitor. The OS can just always be loaded and ready to go; when power is restored it checks to see if the hardware has changed and just loads up the 64 MB of CPU cache. It could take just a few milliseconds. It takes on the order of a millisecond to charge the capacitors in a desktop PSU. "Restarting" becomes basically the same thing as reloading, and takes >100s of times longer than actually restarting the device. That's crazy to consider. If boot time is 0, stuff will just unplug itself after its been idle for a few seconds. I'd expect the hardware in phones/laptops to become more distributed, with basic vital functions handled by a separate processor. Probably the screen gets taken over by a very simple processor that can only display the time, battery %, cell info (or the current screen buffer, for a laptop) and user input causes the main cpu to wake up in between frames.
- benj111 3y ago
  Why do you even need a cpu cache? 1ns write operations suggest fast read too.
  - vlovich123 3y ago
    You’d probably still need an L1 cache. L2 and L3 might be superfluous or you could have massive L2/L3 caches made with this rather than traditional SRAM that sit internally within the CPU to avoid the memory bus. Contention for the memory bus could also be a reason to still have SRAM caches that are slower than main memory. Shifts like this are so impactful it’s hard to predict exactly what good designs will look like until we’ve had 5-10 years hands on for the industry to shake out how the Hw topology will looks like (maybe more since HW dev cycles prevent fast iteration and testing of ideas)
  - hwillis 3y ago
    Should be stressed that speed is entirely theoretical: https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103 https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101... > In all of the above tests, the program and erase states were set using between 1 and 10 ms voltage pulses, two times longer than the switching times used in our recent report of ULTRARAM on GaAs substrates.[15] In both cases, the devices operate at a remarkably high speed for their large (20 μm) feature size. Assuming ideal capacitive scaling[33] down to state-of-the-art feature sizes, the switching performance would be faster than DRAM, although testing on smaller feature size devices is required to confirm this. > Why do you even need a cpu cache? Cell read time is entirely different from latency and throughput. This stuff still reads in rows like RAM and can't just be accessed freely like registers.

tuatoru 3y ago

1/100 power, 1/10 latency... in a through-hole chip carrier?? How do they get enough of it close enough to the CPU at those low powers and latencies, at DRAM clocks? Electricity travels 10cm in a tenth of a nanosecond, best case. And it uses quantum... I'll leave it to the experts.

duskwuff 3y ago
> 1/100 power, 1/10 latency... in a through-hole chip carrier?? That's a common package for testing ICs -- notice the array of dies inside and the haphazardly placed bonding wires. It isn't the final form factor.
alias_neo 3y ago
My understanding, from reading it, is that the through-hole carrier is for demos. I doubt they've actually demonstrated the speed/power claims practically; that's what the new test kit, and potential fab partnerships are for.
Tuna-Fish 3y ago
They are talking about the speed of the new type of memory cell, not of the physical implementation they have it in. If this actually pans out, it will be worthwhile to stack a lot of it on the same package as the CPU. The reason memory is so far in current systems is mainly that having it closer wouldn't actually meaningfully help, because almost all the latency is reading data from the DRAM array anyway. If they suddenly get an economical new memory type that has an access latency of tenth of what DRAM does, they are going to figure out how to get it close enough that the signal travel will not be a meaningful part of the total latency.
- tuatoru 3y ago
  Thank you for the explanation! TIL.

hwillis 3y ago

If they've done that, I think the concept of "turning off" a device goes away. You just unplug it, and the energy needed to dump the stuff in the pipeline to memory can be stored in a capacitor. The OS can just always be loaded and ready to go; when power is restored it checks to see if the hardware has changed and just loads up the 64 MB of CPU cache. It could take just a few milliseconds. It takes on the order of a millisecond to charge the capacitors in a desktop PSU. "Restarting" becomes basically the same thing as reloading, and takes >100s of times longer than actually restarting the device. That's crazy to consider. If boot time is 0, stuff will just unplug itself after its been idle for a few seconds. I'd expect the hardware in phones/laptops to become more distributed, with basic vital functions handled by a separate processor. Probably the screen gets taken over by a very simple processor that can only display the time, battery %, cell info (or the current screen buffer, for a laptop) and user input causes the main cpu to wake up in between frames.

benj111 3y ago
Why do you even need a cpu cache? 1ns write operations suggest fast read too.
- vlovich123 3y ago
  You’d probably still need an L1 cache. L2 and L3 might be superfluous or you could have massive L2/L3 caches made with this rather than traditional SRAM that sit internally within the CPU to avoid the memory bus. Contention for the memory bus could also be a reason to still have SRAM caches that are slower than main memory. Shifts like this are so impactful it’s hard to predict exactly what good designs will look like until we’ve had 5-10 years hands on for the industry to shake out how the Hw topology will looks like (maybe more since HW dev cycles prevent fast iteration and testing of ideas)
- hwillis 3y ago
  Should be stressed that speed is entirely theoretical: https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103 https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101... > In all of the above tests, the program and erase states were set using between 1 and 10 ms voltage pulses, two times longer than the switching times used in our recent report of ULTRARAM on GaAs substrates.[15] In both cases, the devices operate at a remarkably high speed for their large (20 μm) feature size. Assuming ideal capacitive scaling[33] down to state-of-the-art feature sizes, the switching performance would be faster than DRAM, although testing on smaller feature size devices is required to confirm this. > Why do you even need a cpu cache? Cell read time is entirely different from latency and throughput. This stuff still reads in rows like RAM and can't just be accessed freely like registers.