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> Two A510 cores can be clustered and share a L2 cache, FPU, and L2 TLB. Arm calls this a merged core configuration, and hopes it’ll increase area efficiency wi
by bpye 3y ago
> Two A510 cores can be clustered and share a L2 cache, FPU, and L2 TLB. Arm calls this a merged core configuration, and hopes it’ll increase area efficiency with minimal performance impact.
Isn’t this also a lot like what AMD did with Bulldozer?
- skavi 3y agofrom TFA: > Note on Bulldozer > Bulldozer is an obvious comparison because it also shares substantial resources between core pairs. However, shared resources had little to do with Bulldozer’s performance problems. In fact, Bulldozer was most competitive in multithreaded applications where there could be contention for shared resources. Bulldozer issues came from having less per-thread reordering capacity and higher cache latency than Sandy Bridge in a market where single-thread performance was of paramount importance. Cortex A510 does not target the high performance market. If performance did matter A510 would be held back by its in-order execution scheme, not shared resources. Instead of performance, A510 targets low power and area. Sharing resources fits that goal perfectly.
- a-french-anon 3y agoYep, I dare to say that Piledriver wasn't bad at all, when you weren't just needing single-threaded performance. Power consumption was horrid, though.
- hajile 3y agoAMD would have been far ahead of the game if they'd made 1 big ALU, 1 big FPU, and 1-3 little ALUs. They'd have been competitive on single-thread performance while getting a big boost in multithreaded performance without all the complexity of SMT.
- AlotOfReading 3y agoThat's not an inherently terrible thing. Bulldozer did many things wrong that led to that awful performance, it wasn't just the CMT. AMD sacrificed a lot to get the frequencies up, and every other number in the system suffered for it. Worse, the schedulers available at the time weren't smart enough to properly keep the things turboing, so that sacrifice ended up being for naught. ARM is competent enough to avoid the obvious pitfalls there and it's a decent strategy for the what the A5xx series is supposed to be (power efficient/cost-optimized).
- happycube 3y agoSo ironic given how AMD ran circles around intel during the P4 era... and AMD didn't have the things intel had to fall back on when Netburst/Tejas really went off the rails.
- rsaxvc 3y agoArchitecturally similar to Sun S1 cores found in Niagara/T1 chips, when SMT is disabled.
- Symmetry 3y agoThe problem with Bulldozer was mostly the wonky cache hierarchy, not the modularization. Well, the shared front end was a big problem but AMD fixed that in Steamroller and the A510 isn't making that mistake.