don't get seduced - this is nothing more than a (dead) core generator implemented in chisel. it was written back when people thought chisel was gonna take the H

don't get seduced - this is nothing more than a (dead) core generator implemented in chisel. it was written back when people thought chisel was gonna take the HDL world by storm (spoilter alert: it did not). there have been successor projects but imho they're all worthless - no RTL designer worth their salt uses these kinds of tools and instead prefers to write verilog/vhdl.