3 ms·

It's been a long while since I've designed PCB, but doesn't auto-routing provide a good starting point that the designer can refine? I remember it reducing a lo

It's been a long while since I've designed PCB, but doesn't auto-routing provide a good starting point that the designer can refine? I remember it reducing a lot of grunt work.

Alupis 3y ago
It creates more problems than it solves for anything but very trivial layouts. It has no comprehension of the actual components it's placing, or the nets it's routing. So it'll find a physical layout that matches your schematic in a logical sense, but the actual circuit may not work when it's finally assembled (ADC placed next to a switching power supply, for example). Some components have strict tolerances or needs, and some types of designs require special considerations. So, a newbie will click the button to auto-route and then have the board fabricated and then do the final assembly - then wonder why it doesn't work, or it sometimes works, etc. If you don't have the skills and knowledge to do the layout the "right" way, you likely don't have the skills or knowledge to debug a bad board layout. PCB layout is not trivial. Some folks spend an entire career doing just PCB layout. For low-speed trivial designs, you can get away with a lot of bad practices, but it's best to invest some small amount of time learning the craft. However, general rule of thumb, if your design works on a breadboard then you can probably make it work on a PCB... probably.
- aswanson 3y ago
  Adc near a switching power supply made me lol. Some guy at a previous gig did that with 190v pwm motor drives. No autotouter in the loop. Just a bad human.
dragontamer 3y ago
Rats nest is good enough IMO. Just saying "Pin#20 needs to be connected to Pin#88", with a visual indication that they're not connected yet, is plenty. A Rat's nest is more than enough to figure out which parts need to be placed next to each other, at least for beginner boards with like ~50 or fewer components on them (and maybe ~100 or less nets/traces to manage) The issue with PCB-design is that: 1. Even the slowest ~4MHz microcontrollers have 1ns rise/fall times, or 1GHz+ of high-frequency noise all over the place. Faster chips have even faster rise/fall times. 2. ~1GHz wavelength is ~30cm, meaning that a 7.5cm trace is an effective antenna for 1GHz noise. As it turns out, 7.5cm is well within the scope of typical PCB design. A faster rise/fall time (ex: 0.2ns rise/fall time is 5GHz noise instead) could have "antennas" as small as 2.5cm or 25mm. 3. Vias have non-negligible inductance and resistance. Modern signal design also requires the designer to think of "the return path", so a 2nd nearby via to serve as a capacitively-coupled via (IE: "Route a ground-via next to any signal-via"), and other such rules, are rarely followed by autorouters. ------------ It looks like the professional tools are fixing this problem by performing FEA of signals / coupling / electronic flux, and helping the engineer visualize the magnetic and electrical fields of the designed PCB-layout. However, if you are a conservative human, you can get such a feel for your circuit by thinking about return-paths and mentally thinking about microstrips (ex: wire + ground-plane return), or striplines (ex: ground-wire-ground plane for internal layers). The return path is always on the nearby ground plane, so it makes it very easy to think about.
CamperBob2 3y ago
Placement is usually as important as routing, if not more so. At the same time, the act of thinking carefully about placement will often making routing easier. I try to take a holistic view -- I don't see routing as grunt work, or as an unnecessary chore, but as part of the design process. On a long-enough timeline, ML tools will become a natural fit for placement and routing. It is a rather dumb thing for humans to have to deal with, at the end of the day, but the existing tools are just not good enough to take over the job. At least not the tools that most of us have access to.
- dragontamer 3y ago
  Unless ML tools know which nets have how much current/voltages on them, as well as which ones are sensitive to noise... as well as rise/fall times of each pin, its a hopeless job. Lets say you have a trace that's 4mm wide that skips across a slot in the ground-plane. Is this good or bad? 1. Why is it 4mm? Is this a high-current line / power line of some kind? A crude power-plane that's just oversized for a trace? Is this a switching regulator with a bit of switching noise? Or is it a "quiet" power line, like a battery or LDO-line? 2. Is this trace actually ground? And the 4mm is to "jump" across the gnd-slot to provide a controlled return-path for some other line? What is the relationship of this trace vs another trace? ---------- If its a fat line on a switching power supply with a ton of current, maybe its a bad idea. If its a fat gnd, maybe its a good idea. Its all contextual. Its not very clear how a hypothetical ML tool would figure out this context, outside of like learning to read data-sheets and/or the EE writing down the purpose (very precisely) on each net... which probably is slower than just routing the trace manually to begin with.
  - CamperBob2 3y ago
    The tool will have access to the same data sheets and SPICE/IBIS models that you do. It will know what to do. Eventually.
    - dragontamer 3y ago
      Are you going to put the source-code of your programs in there too? I'm not sure how a ML model would ever know that... say... Pin A5 is a rarely-changing GPIO that's effectively DC. Or that Pin-B6 is configured as an analog-DAC in this particular application (and therefore slowly changing). Or hell, that PinC1 is an input vs output. Modern chips have very flexible pins. Many microprocessors (and MCUs) can configure any pin to be input, output, tri-state output, pull-up output, or pull-down output, for example, with different properties in each state. Some pins can be analog (on-board op-amps), others can be digital and high frequency, still others can be digital but rarely-changing / effectively DC for the lifetime of the application. Each scenario changes how you'd route a trace.

It's been a long while since I've designed PCB, but doesn't auto-routing provide a good starting point that the designer can refine? I remember it reducing a lot of grunt work.

Alupis 3y ago

It creates more problems than it solves for anything but very trivial layouts. It has no comprehension of the actual components it's placing, or the nets it's routing. So it'll find a physical layout that matches your schematic in a logical sense, but the actual circuit may not work when it's finally assembled (ADC placed next to a switching power supply, for example). Some components have strict tolerances or needs, and some types of designs require special considerations. So, a newbie will click the button to auto-route and then have the board fabricated and then do the final assembly - then wonder why it doesn't work, or it sometimes works, etc. If you don't have the skills and knowledge to do the layout the "right" way, you likely don't have the skills or knowledge to debug a bad board layout. PCB layout is not trivial. Some folks spend an entire career doing just PCB layout. For low-speed trivial designs, you can get away with a lot of bad practices, but it's best to invest some small amount of time learning the craft. However, general rule of thumb, if your design works on a breadboard then you can probably make it work on a PCB... probably.

aswanson 3y ago
Adc near a switching power supply made me lol. Some guy at a previous gig did that with 190v pwm motor drives. No autotouter in the loop. Just a bad human.

dragontamer 3y ago

Rats nest is good enough IMO. Just saying "Pin#20 needs to be connected to Pin#88", with a visual indication that they're not connected yet, is plenty. A Rat's nest is more than enough to figure out which parts need to be placed next to each other, at least for beginner boards with like ~50 or fewer components on them (and maybe ~100 or less nets/traces to manage) The issue with PCB-design is that: 1. Even the slowest ~4MHz microcontrollers have 1ns rise/fall times, or 1GHz+ of high-frequency noise all over the place. Faster chips have even faster rise/fall times. 2. ~1GHz wavelength is ~30cm, meaning that a 7.5cm trace is an effective antenna for 1GHz noise. As it turns out, 7.5cm is well within the scope of typical PCB design. A faster rise/fall time (ex: 0.2ns rise/fall time is 5GHz noise instead) could have "antennas" as small as 2.5cm or 25mm. 3. Vias have non-negligible inductance and resistance. Modern signal design also requires the designer to think of "the return path", so a 2nd nearby via to serve as a capacitively-coupled via (IE: "Route a ground-via next to any signal-via"), and other such rules, are rarely followed by autorouters. ------------ It looks like the professional tools are fixing this problem by performing FEA of signals / coupling / electronic flux, and helping the engineer visualize the magnetic and electrical fields of the designed PCB-layout. However, if you are a conservative human, you can get such a feel for your circuit by thinking about return-paths and mentally thinking about microstrips (ex: wire + ground-plane return), or striplines (ex: ground-wire-ground plane for internal layers). The return path is always on the nearby ground plane, so it makes it very easy to think about.

CamperBob2 3y ago

Placement is usually as important as routing, if not more so. At the same time, the act of thinking carefully about placement will often making routing easier. I try to take a holistic view -- I don't see routing as grunt work, or as an unnecessary chore, but as part of the design process. On a long-enough timeline, ML tools will become a natural fit for placement and routing. It is a rather dumb thing for humans to have to deal with, at the end of the day, but the existing tools are just not good enough to take over the job. At least not the tools that most of us have access to.

dragontamer 3y ago
Unless ML tools know which nets have how much current/voltages on them, as well as which ones are sensitive to noise... as well as rise/fall times of each pin, its a hopeless job. Lets say you have a trace that's 4mm wide that skips across a slot in the ground-plane. Is this good or bad? 1. Why is it 4mm? Is this a high-current line / power line of some kind? A crude power-plane that's just oversized for a trace? Is this a switching regulator with a bit of switching noise? Or is it a "quiet" power line, like a battery or LDO-line? 2. Is this trace actually ground? And the 4mm is to "jump" across the gnd-slot to provide a controlled return-path for some other line? What is the relationship of this trace vs another trace? ---------- If its a fat line on a switching power supply with a ton of current, maybe its a bad idea. If its a fat gnd, maybe its a good idea. Its all contextual. Its not very clear how a hypothetical ML tool would figure out this context, outside of like learning to read data-sheets and/or the EE writing down the purpose (very precisely) on each net... which probably is slower than just routing the trace manually to begin with.
- CamperBob2 3y ago
  The tool will have access to the same data sheets and SPICE/IBIS models that you do. It will know what to do. Eventually.
  - dragontamer 3y ago
    Are you going to put the source-code of your programs in there too? I'm not sure how a ML model would ever know that... say... Pin A5 is a rarely-changing GPIO that's effectively DC. Or that Pin-B6 is configured as an analog-DAC in this particular application (and therefore slowly changing). Or hell, that PinC1 is an input vs output. Modern chips have very flexible pins. Many microprocessors (and MCUs) can configure any pin to be input, output, tri-state output, pull-up output, or pull-down output, for example, with different properties in each state. Some pins can be analog (on-board op-amps), others can be digital and high frequency, still others can be digital but rarely-changing / effectively DC for the lifetime of the application. Each scenario changes how you'd route a trace.