6 ms·
Do we have a ChatGPT-style workflow for PCBs on the horizon yet?
by kachurovskiy 3y ago
Do we have a ChatGPT-style workflow for PCBs on the horizon yet?
- stn8188 3y agoDefinitely not GPT-style, but there are quite a few examples of ML/AI integration with EDA. For example: Startup looking at a post-layout DFM check workflow: https://cadstrom.io/ https://cadstrom.io/ Cadence is probably the biggest EDA company talking about ML/AI in the PCB space (that I've noticed) with their recently announced "Allegro X" stuff. The videos are mostly marketing fluff, but they seem to be on track with what I'd expect for "AI assisted PCB design". https://www.cadence.com/en_US/home/tools/pcb-design-and-analysis/allegro-x-design-platform.html https://www.cadence.com/en_US/home/tools/pcb-design-and-anal... https://www.youtube.com/watch?v=RlWfSQq0NkA https://www.youtube.com/watch?v=RlWfSQq0NkA They also have a neat machine-learning optimization tool for their electronics simulations: https://www.cadence.com/en_US/home/tools/system-analysis/optimality.html https://www.cadence.com/en_US/home/tools/system-analysis/opt... On the chip-design side of EDA, both Cadence and Synopsys have a bunch of AI-assisted tools that supposedly are being used right now. I'm not as familiar with that stuff so I prefer to read the humorous Deep Chip summaries: http://www.deepchip.com/items/0593-08.html http://www.deepchip.com/items/0593-08.html And lastly, there's some recently published and soon-to-be-published work showing that there's potential to speed up electromagnetic simulations with neural nets. It's all just proof-of-concept for now, but I'm hoping this proves that ML/AI can be can be integrated in a useful manner in commercial electromagnetic solvers :) https://shielddigitaldesign.com/posts/2022/ml-replace-field-solver/ https://shielddigitaldesign.com/posts/2022/ml-replace-field-... https://shielddigitaldesign.com/posts/2023/s-param-from-via/ https://shielddigitaldesign.com/posts/2023/s-param-from-via/
- AdamH12113 3y agoI think there are too many steps with too many opportunities for failure and too little training data for such a thing to be feasible for the foreseeable future. Almost any small error of the kind that GPTs produce can prevent your board from working or destroy components. Picking the wrong part number or connecting the wrong pins is a hard fail that costs a fair bit of time and money to fix. Softer error like picking the wrong capacitor value for an RC filter or using bad trace routing would be tricky to debug. Maybe a better approach would be to have an LLM generate RTL code for an FPGA.
- 4b11b4 3y agoflux.ai
- stn8188 3y agoOh shoot, I forgot about these guys too! :)
- RF_Savage 3y agoFlux.io is attempting something like that.