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Big-endian CPUs were once the dominant clients in TCP/IP networking, and these machines define the hton and ntoh C macros as no-ops. This means that the network
by chasil 3y ago
Big-endian CPUs were once the dominant clients in TCP/IP networking, and these machines define the hton and ntoh C macros as no-ops. This means that the network itself is big-endian.
Here is an old HP-UX machine running on PA-RISC:
# grep ntoh /usr/include/netinet/in.h
#ifndef ntohl
#define ntohl(x) (x)
#define ntohs(x) (x)
On x86_64, this is a byte-swap:
$ grep bswap /usr/include/netinet/*.h
/usr/include/netinet/in.h:# define ntohl(x) __bswap_32 (x)
/usr/include/netinet/in.h:# define ntohs(x) __bswap_16 (x)
/usr/include/netinet/in.h:# define htonl(x) __bswap_32 (x)
/usr/include/netinet/in.h:# define htons(x) __bswap_16 (x)
SPARC is big-endian, and the memory is not in the same order as it is on x86. This can coax bugs out of software that are otherwise not seen on little-endian systems.
Alpha is litte-endian, but it has its own exotic problems.
- KMag 3y ago> Alpha is litte-endian, but it has its own exotic problems. At least some models of the Alpha were bi-endian, selectable via a pin on the package, IIRC. I believe the Cray T3E ran the chips big-endian.
- chasil 3y agoI think MIPS and POWER could also do this.
- my123 3y agoArm (both 32 and 64-bit) supports both BE and LE. Switchable at runtime so that you can have a BE VM on an LE host just fine. Apple Arm chips however are LE only, but all of Arm's Cortex-A/Neoverse and NVIDIA's cores support both LE and BE operation.