> Current cores need predecoders to find instruction boundaries which is just not needed with fixed width instructions The question is, how much overhead does

> Current cores need predecoders to find instruction boundaries which is just not needed with fixed width instructions The question is, how much overhead does it cause compared to the whole picture. There are empirical evidences the answer is "very little": https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-matter/ https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-... > With the op cache disabled via an undocumented MSR, we found that Zen 2’s fetch and decode path consumes around 4-10% more core power, or 0.5-6% more package power than the op cache path. In practice, the decoders will consume an even lower fraction of core or package power.