12 ms·

Intel Meteor Lake Architecture

108 points by SandraBucky 3y ago

thunderbird120 3y ago
Will be interested to see how this first(ish) gen of Intel's disaggregated chips pan out. I've been needing to replace my laptop and these seem like they have the potential to be extremely nice for a mid range machine with long battery life. The new scheduler hierarchy is especially interesting given how much of the physical chip they can avoid powering on at all for most simple tasks. For a lot of light use cases the entire "real" CPU and GPU parts of the silicon can be completely dark since the SOC has two tiny cores to run things and other necessary parts things like the video decode silicon were separated from the GPU.
- brucethemoose2 3y ago
  Eh, I have a sneaking suspicion the compute dies won't be shut down as much as you'd think, and that there will be some extra power usage from crossing the dies like desktop Ryzen parts (though hopefully not nearly as severe). A good Process Lasso config is probably worth the time investment. Instead of "trusting" the scheduler, you could force everything non time sensitive onto the efficiency island, maybe by default.
  - bwhitty 3y ago
    The 3D Foveros packaging technology is critical as it allows some path lengths to be much shorter than if you had to traverse that same path but only in the horizontal 2D plane. Very excited to see how this plays out in practice.
    - brucethemoose2 3y ago
      I thought Meteor Lake was tiled and 2D? Intel has EMIB and such for very good bridges, but they are still bridges. If it is 3D stacked with TSVs, thats a whole other can of worms. AMD's X3D on Ryzen 7000 creates heat/clockspeed issues, and they reportedly canceled a 3D variant of the 7900 GPUs due to similar issues.
- transpute 3y ago
  Disaggregation is also good for risk management of attack surfaces. > Intel has broken out the Silicon Security Engine from its traditional Converged Security and Manageability Engine (CSME). Good to see Security separated from ME. Hopefully the ME no longer has control over IOMMU isolation of devices.
  - sweetjuly 3y ago
    I'm not sure I follow. It's almost guaranteed that all chiplets are still on some global system bus just like they were on their monolithic dies. Unless Intel has taken sudden great strides with their SoC security architecture, there are likely still all the old problems (plus a bunch of new fun ones!). Taking it off die is a response to the physical scaling issue, it's really not meant as a security enhancement.
    - transpute 3y ago
      Per the article, both IP blocks remain within the same SOC chiplet/tile. https://en.wikipedia.org/wiki/Intel_Management_Engine https://en.wikipedia.org/wiki/Intel_Management_Engine > Starting with ME 11, it is based on the Intel Quark x86-based 32-bit CPU and runs the MINIX 3 operating system. If "Silicon Security" functions are now executing on a separate CPU/OS, it's an increase in separation from Intel ME functions. https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/3 https://www.anandtech.com/show/20046/intel-unveils-meteor-la... > [Meteor Lake] introduces the Intel Silicon Security Engine (ISSE), a dedicated component focused solely on securing things at a silicon level ... The Converged Security and Manageability Engine (CSME) has also been partitioned to further enhance platform security.
dschuetz 3y ago
The article (or Intel) do not disclose up to how many cores that new architecture is designed for, and I am certain Intel would say something like "With our P-, E-, LE-cores designed architecture(tm) the core count does matter anymore". Also the SOC with built-in AI engine. Oh boy, I wonder how long it will take for AI-assisted malware, or botnets to emerge. Exciting times!
- karavelov 3y ago
  It's just 6P + 8E + 2IO (ultra efficient) cores or less. Looks it's primary targeting laptops.
  - dylan604 3y ago
    Sounds more like targeting is more of "Apple Silicon is kicking our asses, and this is the best we could do"
    - brucethemoose2 3y ago
      Again, Intel's target market is very different. They are using off the shelf cores that have to be good in everything from netbooks and industrial boxes to server workloads. Apple, meanwhile, is laser targeting high volume, premium, media heavy laptop-ish TDPs and workloads. And they can afford to burn a ton of money on die area, a bleeding edge low power process, and target modest clockspeeds like no one else can.
      - dylan604 3y ago
        this is such a weak argument. just because it's not in a laptop does not mean that a CPU should be accepted as being a horrible waste of electricity. making datacenters as efficient as laptops would not be a bad thing. i'm sure people operating at the scale of AWS and other cloud providers would be beyond happy to see their power bills drop for no loss in performance. i'm guessing their stockholders would be pleased as well.
eBombzor 3y ago
So a more advanced and feature rich version of Ryzen's IO die, with dedicated silicon for AI of course. Can't wait for Microsoft and Intel to team together to make an ultra AI search bar that can finally find files properly like back in Windows 7...
- speed_spread 3y ago
  Instead the AI will be made part of the unkillable core "security" services and actually be used to find ways to reroute Windows telemetry around DNS blockers, autoconnect to all smart appliances in the house and teach the dog to report on your most intimate habits.
  - szszrk 3y ago
    In win11 I am unable to even find apps (properly installed via signed msi) by typing it's full name. Searching for setting screens is also a pain in the ass, especially if you use different language. MS recognizes only their own translation, not the most intuitive text, not English text ... you just have to know
- brucethemoose2 3y ago
  > ultra AI search bar Or you could use literally any other search program that works wonderfully, without the indexing process using an eyebrow raising amount of CPU? Including Microsoft's own shockingly fast file search in VSCode. > feature rich version of Ryzen's IO die The interconnect Intel is using is more expensive/sophisticated than AMD's (but less expensive than the TSVs for the X3D chips), so hopefully its pretty good in laptops? AMD's IO die setup burns tons of idle power, which is why the laptop parts are still monolithic.
  - Voultapher 3y ago
    FYI that VSCode search is powered by ripgrep.
    - brucethemoose2 3y ago
sillywalk 3y ago
I wish Intel would switch to a new code-name scheme. There's been enough "Lakes".
- kookamamie 3y ago
  Amen. Most are incremental upgrades, so all the codenames seem superfluous.
- mariusmg 3y ago
  >There's been enough "Lakes". Yeah, they need to move to rivers now...
  - kazinator 3y ago
    Just as long as they don't go chasing waterfalls, and stick to the above like they used to.
- deleted 3y ago
  [deleted]
- layer8 3y ago
  At least with “Foo Lake” you immediately know it’s an Intel CPU architecture. That a valuable feature. No reason to burn any bridges. ;)
  - colejohnson66 3y ago
    And the Foo Lake refresh would be Bar Lake?
- Havoc 3y ago
  I kinda like it. Some are cool like ice lake. Others quirky like coffee lake
- throw0101a 3y ago
  Or some semblance of order, like alphabetical, so you have some idea of timing / progression.
kwanbix 3y ago
I still wonder how Apple was able to achieve such an incredible performance per watt ratio compared to Intel and AMD. Anybody knows how they let Apple do it?
- Denvercoder9 3y ago
  One big thing is that Apple has (almost) bought out TSMC's N3 node, so they're the only one with chips made on the most advanced manufacturing process available.
- timc3 3y ago
  I don’t know where to begin… There is a lot of material on the internet that is relevant to answering that. What do you mean “how they let Apple do it”. Do you think Intel & AMD could stop them?
  - kridsdale3 3y ago
    Well, in purely military terms, technically Intel and AMD are only a few miles from Apple and their engineering corps is likely far larger. They could all march over there with broadswords if they really wanted to.
    - Mistletoe 3y ago
      The circular design of the HQ makes sense now. https://www.reddit.com/r/castles/comments/4t5w0q/round_vs_square_walls/ https://www.reddit.com/r/castles/comments/4t5w0q/round_vs_sq...
      - garblegarble 3y ago
        Completely off-topic, but: I think the state of the art in castle design (pre modern explosives anyway) was a star/bastion[1], since that allowed defenders to have overlapping firezones, especially useful once an attacker reaches the walls. With a circular design like Apple's HQ, as attackers get closer to the walls fewer and fewer defensive positions can see them until you can only see them from right above. 1: https://en.wikipedia.org/wiki/Bastion_fort https://en.wikipedia.org/wiki/Bastion_fort
MangoCoffee 3y ago
>Meet Meteor Lake’s Tiles isn't "Tile" is basically chiplet? why not just call it chiplet?
- deleted 3y ago
  [deleted]
- Covzire 3y ago
  AFAIK this will be the first chip where multiple processes are combined into one die, at least for consumer devices. AMD's chiplets use separate dies from multiple node processes all on one substrate so maybe they don't want to confuse it with that.
  - monocasa 3y ago
    It isn't on one die; Meteor lake is 4 dies on a substrate. It's probably a lawyer thing like uncertainty over who owns the noun 'chiplet'.
    - Covzire 3y ago
      The interconnect between dies doesn't rely on the substrate though right?
      - wmf 3y ago
        The interposer is the only way the dies can communicate.
- smolder 3y ago
  Best guess is that someone in marketing thinks calling them Tiles will make Intel look better because people won't realize they're just following behind AMD in this respect.
- aurareturn 3y ago
  Not exactly. The tiles have different functions. AMD's chiplet approach glues homogeneous chips together and uses a center chip to control everything.
Havoc 3y ago
Mostly interested in the npu. Most npus are pretty useless for cutting edge ai
kristianp 3y ago
Interesting to see how efficient these are for office/coding (e.g. typing into vscode) tasks. Will the cpu tile be off most of the time or will it take some years before applications and OS are tuned to avoid cpu tile wakeups. Also how good will the p-cores be compared to previous gen? Are the avx-10 instructions going into this generation?
- RaisingSpear 3y ago
  > Are the avx-10 instructions going into this generation? Nope. In fact, it probably won't be in client until after Lunar Lake (2025+).
  - colejohnson66 3y ago
    Per the AVX10.1 Instruction Set Reference, p. 1-2 (355989-001US rev 1.0)[0], AVX10 support will begin with 6th gen Xeon processors (based on Granite Rapids), which are due next year. Client support is not called out, so your guess of Lunar Lake (late 2024-early 2025) is probably a good guess. [0]: https://cdrdv2.intel.com/v1/dl/getContent/784266 https://cdrdv2.intel.com/v1/dl/getContent/784266
    - adrian_b 3y ago
      No, the instruction set supported by Lunar Lake has been published by Intel a few months ago and it is almost the same as that of Arrow Lake S, i.e. without AVX10 or AVX-512 support (Arrow Lake S supports more instructions than Arrow Lake, e.g. it has SHA-512 secure hash instructions). It is likely that Panther Lake, to be launched in 2025, probably in the second half of the year, will be the first Intel CPU supporting the 256-bit subset of the AVX10.2 ISA version. The 2024 Granite Rapids will probably be the only Intel CPU supporting the AVX10.1 ISA version (with full 512-bit support), because all the following will start from AVX10.2.
    - RaisingSpear 3y ago
      AVX10.1 is just Sapphire Rapids' AVX-512 renamed, so arguably SPR (and early Alder Lake) already support AVX10.1, just without declaring the relevant CPUID bits. Client support depends on E-cores supporting it, and Intel have specified that they'll start with AVX10.2. I don't believe that any core has been announced with AVX10.2 support yet, and we the latest we know is Lunar Lake's ISA support.
sva_ 3y ago
Any word on how many TFLOPs that NPU could achieve on the high-end chips?
keepamovin 3y ago
It's a good name. Why didn't they call it Crater Lake tho? https://en.wikipedia.org/wiki/Crater_Lake https://en.wikipedia.org/wiki/Crater_Lake
- carbocation 3y ago
  In case this isn't a joke centered on expectations that this will crater, there are many Intel chipsets with "-Lake" codenames: https://en.wikipedia.org/wiki/List_of_Intel_codenames https://en.wikipedia.org/wiki/List_of_Intel_codenames
  - keepamovin 3y ago
    No, it wasn’t. I didn’t even think of that. But your list of Intel codenames is fantastic. It’s a great resource. Lots of beautiful names in there. Still, I wonder why they haven’t gone with crater lake such a beautiful lake and right in their wheelhouse in terms of geography.
deleted 3y ago
[deleted]
transpute 3y ago
> The “South” IO fabric is ordered, but non-coherent and PCIe-based. It is home to Wi-Fi and Bluetooth, PCI Express connections, Sensing, USB 3/2, Ethernet, the Power Management Controller (PMC), and Security controllers. Does "Sensing" refer to human presence based on camera and radio (Wi-Fi, UWB) imaging? https://lkml.org/lkml/2023/2/12/314 https://lkml.org/lkml/2023/2/12/314 Intel Visual Sensing Controller (IVSC), codenamed "Clover Falls", is a companion chip designed to provide secure and low power vision capability to IA platforms. The primary use case of IVSC is to bring in context awareness. IVSC interfaces directly with the platform main camera sensor via a CSI-2 link and processes the image data with the embedded AI engine. The detected events are sent over I2C to ISH (Intel Sensor Hub) for additional data fusion from multiple sensors. https://www.techpowerup.com/276114/new-intel-visual-sensing-controller-chip-to-give-next-gen-pcs-ability-to-adapt-to-surroundings https://www.techpowerup.com/276114/new-intel-visual-sensing-... The company didn't detail how it goes about this, but technologies already exist to combine visual input from the PC's cameras; radio from the PC's antennas, audio from its mic array; to form a picture of its surroundings. https://community.intel.com/t5/Blogs/Tech-Innovation/Client/Wi-Fi-Sensing-Adding-Sensing-Capability-To-Intel-Wireless/post/1416624 https://community.intel.com/t5/Blogs/Tech-Innovation/Client/... With an initial focus on respiration detection, we hope to extend the technology to detect other physical activities as well. Intel Labs will demonstrate an early prototype of breathing detection ... The solution detects the rhythmic change in CSI due to chest movement during breathing ... The respiration rates gathered by this technology could play an important role in stress detection and other wellness applications.
KingOfCoders 3y ago
Intel is taking two pages from the Apple ARM book: smaller cores but bigger caches (for more performance and less power) and main memory on the chip (for more performance and less power).

108 points by SandraBucky 3y ago

Will be interested to see how this first(ish) gen of Intel's disaggregated chips pan out. I've been needing to replace my laptop and these seem like they have the potential to be extremely nice for a mid range machine with long battery life. The new scheduler hierarchy is especially interesting given how much of the physical chip they can avoid powering on at all for most simple tasks. For a lot of light use cases the entire "real" CPU and GPU parts of the silicon can be completely dark since the SOC has two tiny cores to run things and other necessary parts things like the video decode silicon were separated from the GPU.

brucethemoose2 3y ago
Eh, I have a sneaking suspicion the compute dies won't be shut down as much as you'd think, and that there will be some extra power usage from crossing the dies like desktop Ryzen parts (though hopefully not nearly as severe). A good Process Lasso config is probably worth the time investment. Instead of "trusting" the scheduler, you could force everything non time sensitive onto the efficiency island, maybe by default.
- bwhitty 3y ago
  The 3D Foveros packaging technology is critical as it allows some path lengths to be much shorter than if you had to traverse that same path but only in the horizontal 2D plane. Very excited to see how this plays out in practice.
  - brucethemoose2 3y ago
    I thought Meteor Lake was tiled and 2D? Intel has EMIB and such for very good bridges, but they are still bridges. If it is 3D stacked with TSVs, thats a whole other can of worms. AMD's X3D on Ryzen 7000 creates heat/clockspeed issues, and they reportedly canceled a 3D variant of the 7900 GPUs due to similar issues.
transpute 3y ago
Disaggregation is also good for risk management of attack surfaces. > Intel has broken out the Silicon Security Engine from its traditional Converged Security and Manageability Engine (CSME). Good to see Security separated from ME. Hopefully the ME no longer has control over IOMMU isolation of devices.
- sweetjuly 3y ago
  I'm not sure I follow. It's almost guaranteed that all chiplets are still on some global system bus just like they were on their monolithic dies. Unless Intel has taken sudden great strides with their SoC security architecture, there are likely still all the old problems (plus a bunch of new fun ones!). Taking it off die is a response to the physical scaling issue, it's really not meant as a security enhancement.
  - transpute 3y ago
    Per the article, both IP blocks remain within the same SOC chiplet/tile. https://en.wikipedia.org/wiki/Intel_Management_Engine https://en.wikipedia.org/wiki/Intel_Management_Engine > Starting with ME 11, it is based on the Intel Quark x86-based 32-bit CPU and runs the MINIX 3 operating system. If "Silicon Security" functions are now executing on a separate CPU/OS, it's an increase in separation from Intel ME functions. https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/3 https://www.anandtech.com/show/20046/intel-unveils-meteor-la... > [Meteor Lake] introduces the Intel Silicon Security Engine (ISSE), a dedicated component focused solely on securing things at a silicon level ... The Converged Security and Manageability Engine (CSME) has also been partitioned to further enhance platform security.

dschuetz 3y ago

The article (or Intel) do not disclose up to how many cores that new architecture is designed for, and I am certain Intel would say something like "With our P-, E-, LE-cores designed architecture(tm) the core count does matter anymore". Also the SOC with built-in AI engine. Oh boy, I wonder how long it will take for AI-assisted malware, or botnets to emerge. Exciting times!

karavelov 3y ago
It's just 6P + 8E + 2IO (ultra efficient) cores or less. Looks it's primary targeting laptops.
- dylan604 3y ago
  Sounds more like targeting is more of "Apple Silicon is kicking our asses, and this is the best we could do"
  - brucethemoose2 3y ago
    Again, Intel's target market is very different. They are using off the shelf cores that have to be good in everything from netbooks and industrial boxes to server workloads. Apple, meanwhile, is laser targeting high volume, premium, media heavy laptop-ish TDPs and workloads. And they can afford to burn a ton of money on die area, a bleeding edge low power process, and target modest clockspeeds like no one else can.
    - dylan604 3y ago
      this is such a weak argument. just because it's not in a laptop does not mean that a CPU should be accepted as being a horrible waste of electricity. making datacenters as efficient as laptops would not be a bad thing. i'm sure people operating at the scale of AWS and other cloud providers would be beyond happy to see their power bills drop for no loss in performance. i'm guessing their stockholders would be pleased as well.

eBombzor 3y ago

So a more advanced and feature rich version of Ryzen's IO die, with dedicated silicon for AI of course. Can't wait for Microsoft and Intel to team together to make an ultra AI search bar that can finally find files properly like back in Windows 7...

speed_spread 3y ago
Instead the AI will be made part of the unkillable core "security" services and actually be used to find ways to reroute Windows telemetry around DNS blockers, autoconnect to all smart appliances in the house and teach the dog to report on your most intimate habits.
- szszrk 3y ago
  In win11 I am unable to even find apps (properly installed via signed msi) by typing it's full name. Searching for setting screens is also a pain in the ass, especially if you use different language. MS recognizes only their own translation, not the most intuitive text, not English text ... you just have to know
brucethemoose2 3y ago
> ultra AI search bar Or you could use literally any other search program that works wonderfully, without the indexing process using an eyebrow raising amount of CPU? Including Microsoft's own shockingly fast file search in VSCode. > feature rich version of Ryzen's IO die The interconnect Intel is using is more expensive/sophisticated than AMD's (but less expensive than the TSVs for the X3D chips), so hopefully its pretty good in laptops? AMD's IO die setup burns tons of idle power, which is why the laptop parts are still monolithic.
- Voultapher 3y ago
  FYI that VSCode search is powered by ripgrep.
  - brucethemoose2 3y ago

sillywalk 3y ago

I wish Intel would switch to a new code-name scheme. There's been enough "Lakes".

kookamamie 3y ago
Amen. Most are incremental upgrades, so all the codenames seem superfluous.
mariusmg 3y ago
>There's been enough "Lakes". Yeah, they need to move to rivers now...
- kazinator 3y ago
  Just as long as they don't go chasing waterfalls, and stick to the above like they used to.
deleted 3y ago
[deleted]
layer8 3y ago
At least with “Foo Lake” you immediately know it’s an Intel CPU architecture. That a valuable feature. No reason to burn any bridges. ;)
- colejohnson66 3y ago
  And the Foo Lake refresh would be Bar Lake?
Havoc 3y ago
I kinda like it. Some are cool like ice lake. Others quirky like coffee lake
throw0101a 3y ago
Or some semblance of order, like alphabetical, so you have some idea of timing / progression.

kwanbix 3y ago

I still wonder how Apple was able to achieve such an incredible performance per watt ratio compared to Intel and AMD. Anybody knows how they let Apple do it?

Denvercoder9 3y ago
One big thing is that Apple has (almost) bought out TSMC's N3 node, so they're the only one with chips made on the most advanced manufacturing process available.
timc3 3y ago
I don’t know where to begin… There is a lot of material on the internet that is relevant to answering that. What do you mean “how they let Apple do it”. Do you think Intel & AMD could stop them?
- kridsdale3 3y ago
  Well, in purely military terms, technically Intel and AMD are only a few miles from Apple and their engineering corps is likely far larger. They could all march over there with broadswords if they really wanted to.
  - Mistletoe 3y ago
    The circular design of the HQ makes sense now. https://www.reddit.com/r/castles/comments/4t5w0q/round_vs_square_walls/ https://www.reddit.com/r/castles/comments/4t5w0q/round_vs_sq...
    - garblegarble 3y ago
      Completely off-topic, but: I think the state of the art in castle design (pre modern explosives anyway) was a star/bastion[1], since that allowed defenders to have overlapping firezones, especially useful once an attacker reaches the walls. With a circular design like Apple's HQ, as attackers get closer to the walls fewer and fewer defensive positions can see them until you can only see them from right above. 1: https://en.wikipedia.org/wiki/Bastion_fort https://en.wikipedia.org/wiki/Bastion_fort

MangoCoffee 3y ago

>Meet Meteor Lake’s Tiles isn't "Tile" is basically chiplet? why not just call it chiplet?

deleted 3y ago
[deleted]
Covzire 3y ago
AFAIK this will be the first chip where multiple processes are combined into one die, at least for consumer devices. AMD's chiplets use separate dies from multiple node processes all on one substrate so maybe they don't want to confuse it with that.
- monocasa 3y ago
  It isn't on one die; Meteor lake is 4 dies on a substrate. It's probably a lawyer thing like uncertainty over who owns the noun 'chiplet'.
  - Covzire 3y ago
    The interconnect between dies doesn't rely on the substrate though right?
    - wmf 3y ago
      The interposer is the only way the dies can communicate.
smolder 3y ago
Best guess is that someone in marketing thinks calling them Tiles will make Intel look better because people won't realize they're just following behind AMD in this respect.
aurareturn 3y ago
Not exactly. The tiles have different functions. AMD's chiplet approach glues homogeneous chips together and uses a center chip to control everything.

Havoc 3y ago

Mostly interested in the npu. Most npus are pretty useless for cutting edge ai

kristianp 3y ago

Interesting to see how efficient these are for office/coding (e.g. typing into vscode) tasks. Will the cpu tile be off most of the time or will it take some years before applications and OS are tuned to avoid cpu tile wakeups. Also how good will the p-cores be compared to previous gen? Are the avx-10 instructions going into this generation?

RaisingSpear 3y ago
> Are the avx-10 instructions going into this generation? Nope. In fact, it probably won't be in client until after Lunar Lake (2025+).
- colejohnson66 3y ago
  Per the AVX10.1 Instruction Set Reference, p. 1-2 (355989-001US rev 1.0)[0], AVX10 support will begin with 6th gen Xeon processors (based on Granite Rapids), which are due next year. Client support is not called out, so your guess of Lunar Lake (late 2024-early 2025) is probably a good guess. [0]: https://cdrdv2.intel.com/v1/dl/getContent/784266 https://cdrdv2.intel.com/v1/dl/getContent/784266
  - adrian_b 3y ago
    No, the instruction set supported by Lunar Lake has been published by Intel a few months ago and it is almost the same as that of Arrow Lake S, i.e. without AVX10 or AVX-512 support (Arrow Lake S supports more instructions than Arrow Lake, e.g. it has SHA-512 secure hash instructions). It is likely that Panther Lake, to be launched in 2025, probably in the second half of the year, will be the first Intel CPU supporting the 256-bit subset of the AVX10.2 ISA version. The 2024 Granite Rapids will probably be the only Intel CPU supporting the AVX10.1 ISA version (with full 512-bit support), because all the following will start from AVX10.2.
  - RaisingSpear 3y ago
    AVX10.1 is just Sapphire Rapids' AVX-512 renamed, so arguably SPR (and early Alder Lake) already support AVX10.1, just without declaring the relevant CPUID bits. Client support depends on E-cores supporting it, and Intel have specified that they'll start with AVX10.2. I don't believe that any core has been announced with AVX10.2 support yet, and we the latest we know is Lunar Lake's ISA support.

sva_ 3y ago

Any word on how many TFLOPs that NPU could achieve on the high-end chips?

keepamovin 3y ago

It's a good name. Why didn't they call it Crater Lake tho? https://en.wikipedia.org/wiki/Crater_Lake https://en.wikipedia.org/wiki/Crater_Lake

carbocation 3y ago
In case this isn't a joke centered on expectations that this will crater, there are many Intel chipsets with "-Lake" codenames: https://en.wikipedia.org/wiki/List_of_Intel_codenames https://en.wikipedia.org/wiki/List_of_Intel_codenames
- keepamovin 3y ago
  No, it wasn’t. I didn’t even think of that. But your list of Intel codenames is fantastic. It’s a great resource. Lots of beautiful names in there. Still, I wonder why they haven’t gone with crater lake such a beautiful lake and right in their wheelhouse in terms of geography.

deleted 3y ago

[deleted]

transpute 3y ago

> The “South” IO fabric is ordered, but non-coherent and PCIe-based. It is home to Wi-Fi and Bluetooth, PCI Express connections, Sensing, USB 3/2, Ethernet, the Power Management Controller (PMC), and Security controllers. Does "Sensing" refer to human presence based on camera and radio (Wi-Fi, UWB) imaging? https://lkml.org/lkml/2023/2/12/314 https://lkml.org/lkml/2023/2/12/314 Intel Visual Sensing Controller (IVSC), codenamed "Clover Falls", is a companion chip designed to provide secure and low power vision capability to IA platforms. The primary use case of IVSC is to bring in context awareness. IVSC interfaces directly with the platform main camera sensor via a CSI-2 link and processes the image data with the embedded AI engine. The detected events are sent over I2C to ISH (Intel Sensor Hub) for additional data fusion from multiple sensors. https://www.techpowerup.com/276114/new-intel-visual-sensing-controller-chip-to-give-next-gen-pcs-ability-to-adapt-to-surroundings https://www.techpowerup.com/276114/new-intel-visual-sensing-... The company didn't detail how it goes about this, but technologies already exist to combine visual input from the PC's cameras; radio from the PC's antennas, audio from its mic array; to form a picture of its surroundings. https://community.intel.com/t5/Blogs/Tech-Innovation/Client/Wi-Fi-Sensing-Adding-Sensing-Capability-To-Intel-Wireless/post/1416624 https://community.intel.com/t5/Blogs/Tech-Innovation/Client/... With an initial focus on respiration detection, we hope to extend the technology to detect other physical activities as well. Intel Labs will demonstrate an early prototype of breathing detection ... The solution detects the rhythmic change in CSI due to chest movement during breathing ... The respiration rates gathered by this technology could play an important role in stress detection and other wellness applications.

KingOfCoders 3y ago

Intel is taking two pages from the Apple ARM book: smaller cores but bigger caches (for more performance and less power) and main memory on the chip (for more performance and less power).