>Do the discrete logic gates get woven into an ad-hoc FPGA? Like literally? Wouldn't that require even more chips? Or are you saying that the act of combining

>Do the discrete logic gates get woven into an ad-hoc FPGA? Like literally? Wouldn't that require even more chips? Or are you saying that the act of combining logic chips itself constitutes a 'buggy, poorly specified [FPGA]'? In which case aren't you erasing the distinction between an FPGA and the alternative.