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>Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code. Very strictly speaking, to t
by snvzz 3y ago
>Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code.
Very strictly speaking, to the point where it's true but irrelevant.
RISC-V does have specifications for memory models: RVWMO and Ztso. They are both ratified.
- acdha 3y agoOh, apologies if it sounded like I was trying to say RISC-V doesn't - I was only trying to explain why we use the term “instruction set architecture” as opposed to just “instruction set”.
- snvzz 3y agoBecause the parent was talking about fragmentation, it does not hurt to ensure it is understood that the memory model _is_ standardized in RISC-V.