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>> There are plenty of ISAs you can find freely available today (Open sparc anyone?). The problem is fragmentation… If by "fragmentation" you mean lack of indu

>> There are plenty of ISAs you can find freely available today (Open sparc anyone?). The problem is fragmentation… If by "fragmentation" you mean lack of industry-wide support, then you've answered your own question as to why RISC-V. Most Debian packages can run on it. There is even an Android port to RISC-V. Outside x86 and ARM, the next best supported ISA is RISC-V. Unrelated: why do they call the instruction set an architecture or ISA?

acdha 3y ago
Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code. For example, Apple had to add an extension to their ARM chips which makes stronger guarantees about the order in which memory is written because x86 Mac apps might have dependencies on that which their developers hadn’t been aware of.
- snvzz 3y ago
  >Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code. Very strictly speaking, to the point where it's true but irrelevant. RISC-V does have specifications for memory models: RVWMO and Ztso. They are both ratified.
  - acdha 3y ago
    Oh, apologies if it sounded like I was trying to say RISC-V doesn't - I was only trying to explain why we use the term “instruction set architecture” as opposed to just “instruction set”.
    - snvzz 3y ago
      Because the parent was talking about fragmentation, it does not hurt to ensure it is understood that the memory model _is_ standardized in RISC-V.
brucehoult 3y ago
> Unrelated: why do they call the instruction set an architecture or ISA? In the early days of all of mainframes, minicomputers, and microprocessors companies slapped some hardware design together and then made un an instruction set for it. When the same company made a better, faster, shinier computer a few years later the hardware was completely different and the instruction set was completely different and everyone had to rewrite their software. One of the best-known examples is the Intel 4004, 8008, 8080, 8086 and so on. None of them can run software for either later or earlier chips. Intel was reasonably good at making it not too hard to rewrite old software, but it still had to be done. An Instruction Set ARCHITECTURE is an instruction set that is designed from the outset to be independent of any particular hardware implementation of it, and it is intended to make and sell machines over a long period of time that can all run the same software. Not only that, but with, for example, the IBM System/360 introduced in 1964 they announced six different machines (Models 30, 40, 50, 60, 62, and 70) on the same day, with about a 20:1 "commercial" performance ratio (90:1 for "scientific" use) and a similar range of monthly rental costs (IBM didn't sell them outright). RISC-V is similarly deliberately an Instruction Set Architecture, that works well with a very wide range of implementation techniques and cost/size, all of which can run exactly the same software (at least if it sticks to RV32I / RV64I).

acdha 3y ago

Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code. For example, Apple had to add an extension to their ARM chips which makes stronger guarantees about the order in which memory is written because x86 Mac apps might have dependencies on that which their developers hadn’t been aware of.

snvzz 3y ago
>Strictly speaking an instruction set doesn’t include things like the memory model which you need to know to be able to port code. Very strictly speaking, to the point where it's true but irrelevant. RISC-V does have specifications for memory models: RVWMO and Ztso. They are both ratified.
- acdha 3y ago
  Oh, apologies if it sounded like I was trying to say RISC-V doesn't - I was only trying to explain why we use the term “instruction set architecture” as opposed to just “instruction set”.
  - snvzz 3y ago
    Because the parent was talking about fragmentation, it does not hurt to ensure it is understood that the memory model _is_ standardized in RISC-V.

brucehoult 3y ago

> Unrelated: why do they call the instruction set an architecture or ISA? In the early days of all of mainframes, minicomputers, and microprocessors companies slapped some hardware design together and then made un an instruction set for it. When the same company made a better, faster, shinier computer a few years later the hardware was completely different and the instruction set was completely different and everyone had to rewrite their software. One of the best-known examples is the Intel 4004, 8008, 8080, 8086 and so on. None of them can run software for either later or earlier chips. Intel was reasonably good at making it not too hard to rewrite old software, but it still had to be done. An Instruction Set ARCHITECTURE is an instruction set that is designed from the outset to be independent of any particular hardware implementation of it, and it is intended to make and sell machines over a long period of time that can all run the same software. Not only that, but with, for example, the IBM System/360 introduced in 1964 they announced six different machines (Models 30, 40, 50, 60, 62, and 70) on the same day, with about a 20:1 "commercial" performance ratio (90:1 for "scientific" use) and a similar range of monthly rental costs (IBM didn't sell them outright). RISC-V is similarly deliberately an Instruction Set Architecture, that works well with a very wide range of implementation techniques and cost/size, all of which can run exactly the same software (at least if it sticks to RV32I / RV64I).