The ISA isn't very useful IMO, outside of the compiler framework. The crux of modern chip design is the tradeoff in MHz, peculiarities of Tomasulo's Algorithm

The ISA isn't very useful IMO, outside of the compiler framework. The crux of modern chip design is the tradeoff in MHz, peculiarities of Tomasulo's Algorithm (out of order buffers, tuning sizes and number of pipelines, etc. etc.). Lets take an example: should you have 200 64-bit words in the reorder buffer, or should you have 800 (Apple M2). What's the tradeoffs? How much slower does accessing the reorder buffer get when you need to go from 8-bits to 10-bits to address the various locations? How many multiplication units should you have? I know Intel has 3 of them per core, is that enough? Or do you go IBM Power route and go for like 20 pipelines wide? Etc. etc. etc. ARM Neoverse N2 makes a lot of these decisions, packages them up into an easy moniker ("General Purpose"), and also has customizations towards V-cores (higher performance but bigger) vs E-cores (lower-performance but smaller and more power-efficient). You then make decisions based off of the core as a whole, rather than designing a core. Ex: do you use 128kB of L1 cache? Or 64kB? Do you do L1 / L2 / L3 cache like Intel? Or do you do L1 / L2 cache like Apple? You still need to make these "uncore" decisions, including the important MESI (core-to-core communications: Modified data vs Exclusive data vs Shared data vs Invalid data). Even _IF_ you buy an off-the-shelf core like Neoverse N2, you're no where close to finishing an actual chip yet cause the darn thing can't even talk to RAM yet.