and everyone who made add-in cards had to add jumpers so that they could choose I/O and interrupt addresses that didn't collide, it was a nightmare - PCI (and N

and everyone who made add-in cards had to add jumpers so that they could choose I/O and interrupt addresses that didn't collide, it was a nightmare - PCI (and Nubus before it) solved those problems with forms of geographical addressing, that required meta-data somewhat equivalent to device trees. RISC-V cores start their physical DRAM addresses at different addresses, some at 0, some at an offset close to 0, some way high. Some embedded systems might have SRAM at one address and DRAM at another - any device addresses have to work around that - if you hard code the UART address then you force people to choose where their memory blocks live, it likely also forces the address range in which other embedded devices live (interrupt controllers, timers etc). RISC-V specs define what the various registers look like, but not where they are (other than offsets wrt other registers of the same type). Multi-vendor architectural specs like RISC-V are a careful balance between making sure that things work and leaving the design space free for innovation - RISC-V doesn't carry a lot of baggage from previous systems which is a great thing