A good example is one of the classic Computer Architecture class assignments which is to simulate a cache. So the way that looks is you have a stream of memory

A good example is one of the classic Computer Architecture class assignments which is to simulate a cache. So the way that looks is you have a stream of memory accesses and you "simulate it" by parsing that file and simulating the actions that would be taken. ie: "ok this block would be put in cache. This next access was a hit, this next access was a miss, etc". So then you just count those actions and estimate the performance by tallying all that up. That's the behavioral model part and IRL they do basically the same thing to decide what behavior they actually want the hardware to do. The next step is the circuit-level model done in verilog which actually simulates the logic-gates and does involve viewing a signal at every clock cycle.