4 ms·
not a silicon engineer or even in the same sphere, but here's my guess- feel free to correct me if I'm wrong: Like Arm's big.LITTLE cpu designs, the last few I
by HeWhoLurksLate 3y ago
not a silicon engineer or even in the same sphere, but here's my guess- feel free to correct me if I'm wrong:
Like Arm's big.LITTLE cpu designs, the last few Intel CPU design generations have used heterogenous CPU cores- some more powerful designed for fast execution, and other less powerful ones designed for power efficiency and density. AMD also has heterogenous cores now, too- with it's X3D chips utilizing chiplets with both stacked cache and without.
Unlike how it used to be on x86, where a reasonable approach was to just spread jobs out evenly across all cores, now which core things go to can have a huge impact on speed, with some games running better on the higher cache cores of an X3D chip while others do better with the higher frequencies of the normal ones.
In the future, I believe this will help reshape the backbone of thread scheduling to make it more efficient and have a better understanding of the processor it's working with without necessarily needing a significant amount of engineering work per heterogenous CPU that comes out.
- rbanffy 3y ago> I believe this will help reshape the backbone of thread scheduling to make it more efficient and have a better understanding of the processor it's working with Indeed. Ideally the kernel would intelligently pull processes that have lots of cache misses towards cores with more cache and processes with fewer misses towards cores with higher clocks. And do that with any finite resource that's unevenly distributed across cores, such as vector units and whatever performance counters can inform the scheduler about.