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Intel seems pretty confident that they will be able to get to 11nm in the next 5 years or so. Past that, pure shrinkage of transistors via purely "conventional

Intel seems pretty confident that they will be able to get to 11nm in the next 5 years or so. Past that, pure shrinkage of transistors via purely "conventional" methods will mostly hit a wall, but everyone saw that coming. There's been a lot of work on nanoelectronics. For example, some scientists recently announced at a semiconductor conference that they had found a way to bypass the diffraction limit completely, making 2nm features with a 650nm laser. Similarly, I know an engineer who worked on a massively-parallel electron-beam-based etching device, which could also be applied similarly at very small node sizes. There's a billion other technical challenges, but there's been a lot of progress in making features on the molecular level. If anything, this is better than expected: EUV has had some serious problems over the past few years, yet its delay hasn't stopped the next few nodes. Moore's law doesn't require that shrinkage continuing, though, as there are other technologies available. Memristors in particular may allow scaling faster than Moore's law would otherwise predict.

jacquesm 15y ago
And then there is the third dimension to consider: http://spectrum.ieee.org/semiconductors/devices/3d-chips-grow-up http://spectrum.ieee.org/semiconductors/devices/3d-chips-gro... That comes with a very large set of engineering challenges but if those are overcome you can expect another big jump.
- marshray 15y ago
  You still have the problem of dumping the additional heat. So AFAICT, 3D will only provide some incremental advancement.
  - reitzensteinm 15y ago
    Plus, even if cooling between layers were figured out, we'll probably just end up with lots of transistors that we can't all power on at once, since we're already at practical power draw limits for most devices. We don't just need to cram more transistors on a chip, we need those transistors to use proportionally less power (preferably even less than that).
  - DarkShikari 15y ago
    There are many ways to dramatically lower power usage if you're willing to accept slower speeds. Intel has recently demoed some extremely low-voltage transistors that used power in the microwatts. You can make up for this dramatically lower speed by adding far more circuitry using 3D chip-stacking. Another possible solution is to use 3D chip stacking to add dedicated hardware for a wide variety of tasks, most of which is turned off when not being used.
  - ippisl 15y ago
    There's the intermediate step to 3D - 2.5D. it's when you lay all you dies side by side, on another chip, instead of a pcb. It makes relatively easy to manage heat and you can get much more bandwidth at much lower power(much shorter wire distances). And it's already in use for high end fpga's.
    - marshray 15y ago
      You mean the multi-chip module (MCM) ? https://en.wikipedia.org/wiki/Multi-Chip_Module https://en.wikipedia.org/wiki/Multi-Chip_Module Those have been around forever. Or something different?
      - jacquesm 15y ago
        He's talking about this: http://www.eetimes.com/electronics-blogs/other/4210170/Xilinx-multi-FPGA-provides-mega-boost-re-capacity--performance--and-power-efficiency- http://www.eetimes.com/electronics-blogs/other/4210170/Xilin...
        marshray 15y ago
        Cool! Thanks. I wonder if the price will ever come down to the point where it's used in consumer devices.

jacquesm 15y ago

And then there is the third dimension to consider: http://spectrum.ieee.org/semiconductors/devices/3d-chips-grow-up http://spectrum.ieee.org/semiconductors/devices/3d-chips-gro... That comes with a very large set of engineering challenges but if those are overcome you can expect another big jump.

marshray 15y ago
You still have the problem of dumping the additional heat. So AFAICT, 3D will only provide some incremental advancement.
- reitzensteinm 15y ago
  Plus, even if cooling between layers were figured out, we'll probably just end up with lots of transistors that we can't all power on at once, since we're already at practical power draw limits for most devices. We don't just need to cram more transistors on a chip, we need those transistors to use proportionally less power (preferably even less than that).
- DarkShikari 15y ago
  There are many ways to dramatically lower power usage if you're willing to accept slower speeds. Intel has recently demoed some extremely low-voltage transistors that used power in the microwatts. You can make up for this dramatically lower speed by adding far more circuitry using 3D chip-stacking. Another possible solution is to use 3D chip stacking to add dedicated hardware for a wide variety of tasks, most of which is turned off when not being used.
- ippisl 15y ago
  There's the intermediate step to 3D - 2.5D. it's when you lay all you dies side by side, on another chip, instead of a pcb. It makes relatively easy to manage heat and you can get much more bandwidth at much lower power(much shorter wire distances). And it's already in use for high end fpga's.
  - marshray 15y ago
    You mean the multi-chip module (MCM) ? https://en.wikipedia.org/wiki/Multi-Chip_Module https://en.wikipedia.org/wiki/Multi-Chip_Module Those have been around forever. Or something different?
    - jacquesm 15y ago
      He's talking about this: http://www.eetimes.com/electronics-blogs/other/4210170/Xilinx-multi-FPGA-provides-mega-boost-re-capacity--performance--and-power-efficiency- http://www.eetimes.com/electronics-blogs/other/4210170/Xilin...
      - marshray 15y ago
        Cool! Thanks. I wonder if the price will ever come down to the point where it's used in consumer devices.