5 ms·
Also the RISC-V ABI requires that the initial code passes a pointer to a minimal device tree to OpenSBI - this means it can tell it where the UART is, how many
by Taniwha 3y ago
Also the RISC-V ABI requires that the initial code passes a pointer to a minimal device tree to OpenSBI - this means it can tell it where the UART is, how many CPUs to expect, where the interrupt controllers are (and what type they are) etc etc - this can then be passed on to uboot/uefi/linux or overridden or edited as they like
- xxpor 3y agoDoes that mean RISC-V doesn't support ACPI at all, even in theory?
- snvzz 3y agoThere's a RISC-V ACPI spec[0]. Note anything to do with ACPI would run after, not before, OpenSBI. 0. https://github.com/riscv-non-isa/riscv-acpi/releases https://github.com/riscv-non-isa/riscv-acpi/releases
- xxpor 3y agoAh, I was thinking OpenSBI was more like the ME for RISC-V, I probably should have googled it.
- rwmj 3y agoYes there's ACPI & UEFI. Sunil V L from Ventana has been gradually pushing ECRs through the ACPI organization to add features and getting the corresponding stuff into the Linux kernel, eg: https://lore.kernel.org/lkml/20230216182043.1946553-4-sunilvl@ventanamicro.com/ https://lore.kernel.org/lkml/20230216182043.1946553-4-sunilv...
- codedokode 3y agoWhy cannot UART address be fixed by a standard? Is there any merit in having UART at different addresses on different machines?
- wazzaps 3y agoWhat if you have no UARTs? Multiple UARTs?
- codedokode 3y agoYou can reserve multiple addresses. 64-bit address space is not small. And even 32-bit address space is huge.
- brucehoult 3y agoOnly if you think of it in advance, when you fix the standard for where everything goes. But how many UARTs should you allow for? 2? 16? 256? No matter what you choose, someone many want to build a system with more, and if you choose 256 (or more) then that's getting to be significant wasted address space for people who only have one UART. All the more so for things that use a lot more address space than half a dozen control registers for a UART. What about 4k (3840x2560) x32 bit frame buffers? Those are 37.5 MB each. Some people want one. Some people want to drive a wall of monitors. Much more flexible to let people configure their address space how they want and supply a devicetree in ROM / SPI flash etc.
- snvzz 3y ago>Is there any merit in having UART at different addresses on different machines? Is there any advantage to encumbering the ISA by having a fixed memory address? If what you need is a debug console, use SBI Debug Console Extension[0]. Otherwise, get the address from the device tree, or from the pointer you've been passed by the SPL, if you are the SBI or you run without SBI. Note that, in the first place, you will be accessing the UART registers using a register as base + an offset. 0. https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-console.adoc https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/s...
- codedokode 3y ago> Is there any advantage to encumbering the ISA by having a fixed memory address? The software becomes much simpler. No need to parse any device trees. When something changes (for example, 128-bit quantum memory becomes available), simply make revision 2 for standard and move device addresses to other place.
- bradleyishungry 3y agoThis is mentioned in the article but under the “intentionally skipped details” section. I’m just starting to learn risc-v, but I assume pointing a1 to the device tree would be all you have to do to pass it to OpenSBI.
- Taniwha 3y agoyes, but you do have to put it somewhere that normal load/stores can reach it, which probably means it's copied to DRAM