4 ms·
I'm not saying that the supported lmul varies. I'm saying that the different cores will break up the same instructions into bigger or smaller execution unit uni
by adgjlsfhk1 3y ago
I'm not saying that the supported lmul varies. I'm saying that the different cores will break up the same instructions into bigger or smaller execution unit units.
- RaisingSpear 3y agoThere's nothing inherent with RVV or LMUL which makes this any easier/harder than other ISAs. Intel could design their little cores to break AVX-512 instructions into 4x128b parts if they felt like it, for example.
- adgjlsfhk1 3y agoThat's technically true, but it means that the best way of handling vector instructions on little cores is something you were going to do anyway.
- RaisingSpear 3y agoSorry, I don't quite understand you there - what is the "something" you speak of, and who does "you" refer to?